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Alternative PoP with photoimageable dielectric material

IP.com Disclosure Number: IPCOM000248224D
Publication Date: 2016-Nov-10
Document File: 3 page(s) / 315K

Publishing Venue

The IP.com Prior Art Database

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

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Alternative PoP with photoimageable dielectric material


A common semiconductor device arrangement includes an upper semiconductor package stacked over a lower semiconductor package, i.e. package-on-package (PoP). The upper semiconductor package is typically electrically connected to the lower semiconductor package with solder ball, copper post, or copper core solder ball (CCSB). A need exists for lower manufacturing cost and lower pitch for high performance.

The invention discloses encapsulation with PID and forming copper post for vertical interconnection. Encapsulation with PID and photo patterning is employed to form openings. The openings are filled with conductive material such that the Cu-post is formed. In addition, PID can be applied to redistribution layer (RDL) on the top surface of PoP. The RDL can interconnect other package devices, which are electrically connected to the bottom package.


Fig. 2 ~ Fig. 8 shows one embodiment of manufacturing process.

Fig. 2 shows chip attach phase. A substrate is provided. A semiconductor chip is disposed on the substrate and electrically connected to the substrate by bumps. Protect material such as underfill, epoxy or epoxy compounds may be disposed on the bumps to protect the bumps from external environment.

Fig. 3 shows PID material coating phase. PID material characteristic is similar with solder resist which is generally used to protect outer surface of a substrate. PID can be patterned by photo, at which portion exposed by photo is rigid. In addition, it can be more hardened by UV or thermal treatment.

Page 02 of 3

Alternative PoP with photoimageable dielectric material

A PID layer is deposited over the substrate so as to cover or encapsulate the semiconductor chip and top surface of the substrate.

Fig. 4 shows forming openings phase. A plurality of opening is formed through PID layer down to top surface of the substrate using a photo patterning process. A mask layer (dry film is preferable) is laminated on the PID encapsulation, at which is needed to form opening. The mask is patterned to form opening for Cu-Post. The PID that is not covered by the mask is exposed to ultraviolet light (UV). The portion of PID exposed by the UV has been developed. After exposure, the mask and the developed portion of...