Browse Prior Art Database

A Method for Mitigating On-Chip Supply Voltage Noise by Boosting the Supply Voltage through Capacitive Coupling

IP.com Disclosure Number: IPCOM000248242D
Publication Date: 2016-Nov-10
Document File: 3 page(s) / 60K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to mitigate the effect of on-chip power-supply noise by preventing timing failure in the case of large and sudden increases in supply current. The method uses a slope-based critical path monitor dedicated to each sensitive block to detect an upcoming droop in the supply voltage, and uses capacitive coupling to temporarily increase the local supply voltage of the sensitive macro/circuits when a voltage droop is detected.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 3

A Method for Mitigating On -

-Chip Supply Voltage Noise by Boosting the Supply

Chip Supply Voltage Noise by Boosting the Supply

Voltage through Capacitive Coupling

Currently, droops are detected and mitigated at a per-core basis. Large delays are associated with this process, mainly due to the need to transfer signals across large distances and the process of combining many signals coming from multiple sensors. During these delays, the supply further droops and the functionality of certain sensitive structures (e.g., arrays) may be compromised.

Conventional mitigation techniques such as adaptive voltage or instruction throttling are employed in a coarse-level scheme (e.g., at each core). Therefore, a large latency is present. By the time these techniques activate, the sensitive circuits may have already failed.

A method is needed to prevent the sensitive circuits from failing until the conventional mitigation techniques activate.

Figure 1: Current state-of-the-art droop detection & mitigation

The proposed solution mitigates the effect of on-chip power-supply noise by preventing timing failure in the case of large and sudden increases in supply current. The novel contribution is a method to use a slope-based critical path monitor dedicated to each sensitive block (e.g., a static random access memory (SRAM)) to detect an upcoming droop in the supply voltage, and to use capacitive coupling to temporarily increase the local supply voltage of the sensitive macro/circuits when a voltage droop is detected. This reduces the power consumption of a processor chip by reducing the applied volta...