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Low warpage prestack MeP with support bar interposer

IP.com Disclosure Number: IPCOM000248249D
Publication Date: 2016-Nov-11
Document File: 4 page(s) / 318K

Publishing Venue

The IP.com Prior Art Database

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 42% of the total text.

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Low warpage prestack MeP with support bar interposer

Background

Various Package-on-package (PoP) structures have been developed for many applications, such as hand phones and other portable devices in which the circuit board space is limited. In the PoP structure, the top package is typically a memory package whereas the bottom package is a processor package. The PoP technology is more preferred to the stacked-die circuit technology, since different memory packages can be substituted in a PoP circuit. In addition, the top and bottom packages can be tested independently, which lowers down the manufacture cost.

The PoP technology faces a major challenge of reducing the interconnect pitch between the top package and the bottom package. The bus width between the top and the bottom packages increases continuously, but the interconnect pitch between the top and the bottom substrates can only accommodate a certain number of signals. The Molded-embedded PoP (MeP) technology has been raised to solve the small-pitch requirement. In the MeP structure shown in Fig. 1, an additional interposer may be included on the bottom package. The additional interposer can redistribute signals to accommodate signals to and from the dies in the top package. In Fig. 1, solder balls are embedded after molding and adopted as interconnects with the bottom portion connected to the laminate substrate and top portion connected to the interposer.

Fig. 1 A Molded-embedded PoP (MeP) structure with a laminate interposer on the bottom package

However, interposer warpage during the conventional reflow processes may result in non- wetting of solder balls and/or bridging between solder joints, and thus decrease the assembly yield. The influence becomes more significant when the chip size increases and the interposer thickness decreases. In Fig. 2 for current interposer attached MEP, the top memory pre-stack issue is shown as an uneven interposer top ball land surface due to unequaled solder ball collapse height or interposer warpage.

Fig. 2 The interposer warpage issue in MeP package

Description

This invention discloses a warpage enhanced MeP package with solder resist (SR) or embedded molding compound (EMC) pillars and support bars. Shown in Fig. 3, the


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Low warpage prestack MeP with support bar interposer

interposer can be a molded interconnect substrate (MIS) or a laminate substrate, which includes EMC or SR pillars mounted on the interposer adhesive at the left and right ends, copper posts mounted on the compressed solder balls at the peripheries next to the pillars, and EMC or SR support bars mounted on the embedded chip at the center of the package. In particular, the SR or EMC support bars and pillars are designed on all of the four corners of package edge for thermal release. The SR or EMC support bars and pillars are separated during package saw process.

The subject invention solves non-wet and/or bridge issues during interposer attachment and pre-s...