Browse Prior Art Database

Gate Cut after Replacement Metal Gate with Air Gap Formation

IP.com Disclosure Number: IPCOM000248270D
Publication Date: 2016-Nov-14
Document File: 5 page(s) / 137K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to utilize a gate cut process and air gap formation between cut gates to improve the process of gate cut formation during dummy gate formation.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 52% of the total text.

Page 01 of 5

Gate Cut after Replacement Metal Gate with Air Gap Formation

Gate cut (CT) during dummy gate (PC) formation has many drawbacks for high density scaling. These include, but are not limited to epitaxy (EPI) merging around the cut end line in static random access memory (SRAM) cells, increased risk for EPI nodule growth on the exposed gate corners during spacer reactive ion etching (RIE), and source/drain contact to gate contact shorting when forming front-end-of-line (FEOL) local interconnects between sets of fins, etc.

Gate cut prior to replacement metal gate (RMG) has scaling penalties, such as containing high-k oxide and work function metal (WFM) thickness on the sidewall of the gate cut regions (2 x thickness - each side of liner fill in the trench) -- space which could be used for scaling. Removal of dummy silicon (dummy gate removal prior to RMG or dummy Silicon (Si) strip after reliability anneal) is hindered if the spacing is too small between the fin end and the cut region. This can lead to residual Si in the gate past fin region to degrade gate electrostatics, drive current and leakage.

Gate cut last in RMG module keeps gate lines continuous and then patterns/cuts those lines into desired shapes. This allows adequate coverage of high-k/WFM on the edge fins near the cut region. Gate cut regions do not include high-k/WFM thicknesses on the sidewalls, so valuable area (2x oxide thickness + 2x WFM thickness) is gained for further scaling.

Performance and circuit delay is limited by parasitic capacitances. Currently, the space between cut gates is filled with Silicon Dioxide (SiO2) (k ~ 3.9) or Silicon Nitride (SiN) (k ~7.5). SiN is primarily used to prevent recess during source/drain contact RIE (oxide RIE). A metal gate cut process that forms an air gap (k ~ 1) between gates during trench fill would reduce this parasitic capacitance for AC performance.

The novel solution is to utilize a gate cut process and air gap formation between cut gates. This includes gate cut lithography and patterning. The approach uses CT after RMG formation, gate WFM/bulk metal recess, and self-aligned contact (SAC) cap deposition. The gate cut after RMG metal recess results in the formation of an SAC cap and "air gap" formation/pinch-off in the cut trench in the same processing step.

The core novelty of the solution is the air gap formation between cut metal gates for low-k dielectric. The selective etch stop layer after the dielectric pinch off (if required) prevents exposure of the cavity during contact RIE (gate or contact overlap). This can be executed in two embodiments:


1. Gate cut post SAC Cap CMP


2. Gate cut post W recess

The steps for implementing the solution in a preferred...