Low-Power High-Performance System on Chip having Silicon FETs for Logic/Memory and High-Mobility FETs for I/O Devices
Publication Date: 2016-Nov-14
The IP.com Prior Art Database
Disclosed is a system on chip (SoC) structure comprising Si or Silicon Germanium (SiGe) fins for logic and memory cells in the fin or gate-all-around architecture, which uses planar III-V channel is used in negative Field Effect Transistors (nFETs) for input/output (I/O) and periphery devices that require a longer gate length and thicker oxide.
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Low- and High-
III-V Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) have shown attractive long to medium channel behavior, outperforming Silicon (Si) MOSFETs. However, for short channel devices, with controlled short channel effects using a FinFET structure, the reported data to date are not outperforming Si due to lack of inversion capacitance and mobility at scaled fin dimensions.
The hetero-integration of high mobility channel materials such as III-V in aggressive ground-rules needed for 5nm and beyond is very challenging, in addition to typical high contact resistivity of III-V FETs, which may overshadow the potential intrinsic performance of III-V FETs.
The novel contribution is a system on chip (SoC) structure comprising Si or Silicon Germanium (SiGe) fins for logic and memory cells (e.g., static random access memory (SRAM), etc.) in the fin or gate-all-around architecture, where for input/output (I/O) and periphery devices that require longer gate length and thicker oxide, planar III-V channel is used in nFET. III-V I/O devices can be made by confined lateral epitaxy either on the same level as other devices or three-dimensional (3D) monolithic on top of pFET I/Os. The pFET I/Os are high mobility long channel strained SiGe with a Ge fraction in the range of 25% to 75%. I/O devices can be planar or trigate or combinations.
This solution ensures that processes take full advantage of high mobility material for long channel devices where mobilit...