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Through Silicon Via (TSV) Application with Stepped Interposer PoP

IP.com Disclosure Number: IPCOM000248391D
Publication Date: 2016-Nov-24
Document File: 3 page(s) / 217K

Publishing Venue

The IP.com Prior Art Database

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Through Silicon Via (TSV) Application with Stepped Interposer PoP

Background

A common semiconductor device arrangement includes an upper semiconductor package stacked over a lower semiconductor package, i.e. package-on-package (PoP). The upper semiconductor package is typically electrically connected to the lower semiconductor package. Recently, a substrate having a stepped feature is emerged to reduce whole package height.

Description

Disclosed is a PoP having a stepped interposer with through silicon via (TSV) semiconductor chips for stacking high I/O device for higher performance. A stepped interposer allows that a semiconductor chip to be placed inside of the interposer, so that the whole package height can be reduced. Also the interposer allows solder ball for interconnecting top package instead of Cu post for increasing I/O, so that the manufacturing cost is lower. The semiconductor chip can include TSV, which can interconnect the substrate to the top package. The increased I/O can accept high I/O devices such as high densification memory. Eventually, electrical performance of the package is improved.

Fig. 1 shows one of embodiments of disclosed package structure. For bottom package, a substrate is provided. The substrate is general laminate substrate to allow semiconductor chip for interconnecting with external device. The TSV semiconductor chip is disposed on the substrate. The chip includes a bump, which can includes Cu, solder, Ni, Au, or combination thereof. The semiconductor chip includes TSV. The TSV semiconductor chip is electrically connected to the substrate by the bump.

For top package, a stepped interposer is provided. The second semiconductor chip is attached on the top surface of the stepped interposer. Connecting wire can interconnect the second semiconductor chip to the stepped interposer. The second semiconductor chip is electrically connected to the stepped interposer. Encapsulant covers over the semiconductor chip and the


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Through Silicon Via (TSV) Application with Stepped Interposer PoP

top surface of the stepped interposer. The top balls (solder balls) are attached on the bottom side of the stepped interposer.

For assembling the bottom package and top package, the top package is disposed on the bottom package. The stepped interposer is electrically connected to the substrate and semiconductor chip by top balls. The stepped feature of the stepped interposer matches position of the TSV semiconductor chip, which is surrounded by the stepped interposer. The bottom solder ball is attached on the bottom surface of the substrate.

Fig. 2 ~ 11 shows manufacturing method of making a stepped interposer.

Referring now to Fig. 2, providing a carrier (detach core) phase. The carrier can include core, a carrier top side metal and a carrier bottom side metal. The cor...