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Protruded Bond on Line (BoL) Pad Layer on embedded trace substrate (ETS, EPL)

IP.com Disclosure Number: IPCOM000248400D
Publication Date: 2016-Nov-25
Document File: 8 page(s) / 492K

Publishing Venue

The IP.com Prior Art Database

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 24% of the total text.

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Protruded Bond on Line (BoL) Pad Layer on embedded trace substrate (ETS, EPL)

Background

Disclosed is an Embedded Trace Substrate (ETS) having copper (Cu) columns on embedded bump pads and manufacturing method of thereof. A semiconductor package substrate includes an upper circuit layer having embedded trace and a plurality of Cu-column. The Cu- column is disposed on and project upward from the upper circuit layer. The Cu-column provides an electrical interconnect to a semiconductor die. Benefits are short failure is reduced, fine pitch applicable, and cost reduction.

Fig. 2 shows comparison of conventional structure and our disclosed structure. In conventional ETS, solder bumps of semiconductor chip are disposed on the embedded pads of a substrate. The solder joint is not reliable because the contacting surface is flat. The wetting failure often occurs. In order to solve the problems, our disclosure suggests Cu- column is projected upward from the embedded bump pad. The contacting surface between a solder bump and a Cu-column is increased, so that the contacting force is increased. The solder joint formed between solder and Cu-column is secured.

Description

Fig. 3 ~ 13 show one embodiment and cross sectional view of manufacturing process of a substrate.


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Protruded Bond on Line (BoL) Pad Layer on embedded trace substrate (ETS, EPL)

Fig. 3 shows a preparation phase of manufacture. A carrier is provided. The carrier includes a core material such as epoxy, fiberglass, glass fabric, resin, a dielectric, insulation material, or a combination thereof. The carrier includes the first copper layer, which is laminated top and bottom surface of the core. The first copper layer can be detachable.

Fig. 4 shows Cu-column patterning phase. A photoresist is directly applied to top and bottom layer (bottom layer is not shown in the figures) of the carrier and then photoresist top layer and the photoresist bottom layer is applied to form a pattern top mask and a pattern bottom mask, respectively. The photoresist material can be a photo-sensitive material such as a photopolymer, resin, dry film, dry film laminate, or combination thereof. The photoresist top layer and the photoresist bottom layer can be patterned to form holes. After patterning, both photoresist layers can be cured to set the material.

Next, plating Cu-column is directly applied to the first copper layer and within the holes. Forming the Cu-column can include forming the component attachment pads in the holes.

Fig. 5 shows first metal layer (M1 layer) patterning phase. The second copper layer is formed on the top and bottom Cu-column layer. A photoresist is directly applied to top and bottom layer (bottom layer is not shown in the figures) of the second copper layer and then photoresist top layer and the photoresist bottom layer is applied to form a pattern top mask and a pattern bottom mask, respectively. The photoresist top layer and the photoresist bottom


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