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Embedded Trace in Stepped Laminate Interposer for Warpage Control

IP.com Disclosure Number: IPCOM000248401D
Publication Date: 2016-Nov-25
Document File: 5 page(s) / 991K

Publishing Venue

The IP.com Prior Art Database

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 01 of 5

Embedded Trace in Stepped Laminate Interposer for Warpage Control

Background

Stepped Interposer PoP is giving a solution for a thinner PoP integrated package structure to use thicker IC chip, such that the attached IC chip on the subs

stepped opening created in the underlying interposer. The use of
interposer would narrow the distance or gap in between the contact pads of interposer with the contact pads of substrate, thus smaller conductive bumps can be used to electrica couple the interposer and substrate in PoP structure. This addressed its advantage for higher density of I/O count and flexibility of design.

However, conventional stepped interposer has encountered warpage concern during PoP

assembly due to interposer asymmetric structure with
vias are devised to locate only around the edge outside of
interposer. This structure could lead to interposer warpage after subjecting to thermal stress,

and cause the solder ball non-wetting issue during assembly as illustrated in Figure 1A. The qualitative occurrence lies on the severity of warpage, which varies the gap in between the conductive pads of the interposer and the substrate.

This invention discloses a viable solution to improve the warpage performance by embedding Cu vias in the cavity. It is contributing to balance the metal density in the interposer structure for the leverage on CTE mismatch, while it shorten the routing distance as shown in Figur

2A.

trate is positioned within the stepped opening

stepped opening feature, and the Cu

stepped opening area of the

within

the contact pads of substrate, thus smaller conductive bumps can be used to electrically

e

Figure 1A: Prior art - Stepped interposer using in PoP structure with

Figure 2A: New invention - Interposer with embedded Cu vias in

solder ball non-wet issue due to warpage

stepped opening


Page 02 of 5

Embedded Trace in Stepped Laminate Interposer for Warpage Control

Description

The process flow for interposer with embedded Cu vias in
preparation of detachable core foil carrier as shown in Figure 3A, whereby the top and

bottom surfaces are processed concurrently. On each side, there consisted o
Cu foil as conductive base structure of interposer. A dry film layer for the
patterning is laminated and developed on both side of the carrier as given in Figure 3B. The Cu plating such as electroless Cu plating is carrie
followed by the dry film stripping process. The formations of
presented from the open areas after the dry film stripping as shown in Figure 3C. Next, a

layer of dry film for the 2nd Cu layer plating

formed 1st Cu layers as depicted in Figure 3D. The Cu plating is proceeded to plate over t...