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Panel Level eWLB PoP with Interposer

IP.com Disclosure Number: IPCOM000248424D
Publication Date: 2016-Nov-28
Document File: 5 page(s) / 413K

Publishing Venue

The IP.com Prior Art Database

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 44% of the total text.

Page 01 of 5

Panel Level eWLB PoP with Interposer

Background

Conventional 3D embedded Wafer Level Ball Grid Array Package on Package (eWLB-PoP) structure is developed in Fig. 1. A chip is embedded inside molding compound, one redistribution layer (RDL) is built on the top side and another RDL is built on the bottom side, and conductive filled vias are formed to electrically connect the top side RDL and the bottom side RDL.

Figure 1:Prior art - Conventional 3D eWLB-PoP

However, the conventional structure has several disadvantages due to complicated process flow and high manufacture cost, such as compression molding process, laser drilling process and top side RDL process.

Description

This invention discloses a eWLB-PoP with an interposer for high bandwidth PoP solution in Fig. 2. Compared with the conventional 3D eWLB-PoP structure, the subject invention has several major improvements: first, the subjection invention introduces a substrate interposer with copper posts plated or copper ball mounted at peripheries, instead of the top side RDL in the conventional structure; second, the subject invention adopts build-up film, including ABF, D/F, PPG, PID or other suitable build-up insulating materials, instead of the compression mold with liquid mold compound in the conventional process; third, the subject invention is suitable for panel level eWLB with build-up film, while the conventional method is limited to wafer level or strip level eWLB.

Figure 2: the structure of the subject invention


Page 02 of 5

Panel Level eWLB PoP with Interposer

The first embodiment of the subject invention is shown in Fig. 3. First, a chip is mounted on a carrier with contact pads in direct contact with the tape. Second, a build-up film lamination is formed on the top of the carrier. Third, a substrate interposer is prepared with copper posts on the peripheries. Forth, the subject interposer is mounted on the build-up film under heat and pressure, with the copper posts completely embedded inside the build-up film; and then the chip is located between the copper posts. Fifth, the carrier with tape is removed from the bottom and thus the top sides of the copper posts and the chip are exposed; and then the structure is inverted for the following processes. Sixth, a RDL is formed on the top, which is electrically connected to the chip and also connected to the substrate interposer through the copper posts. Seventh, solder balls are mounted on the top of the RDL and finally a singulation process is conducted.

Figure 3: the process flow of the first embodiment of the subject invention

The second embodiment of the subject invention is shown in Fig. 4. First, a chip is mounted on a carrier with contact pads in direct contact with the tape. Second, a substrate interposer is prepared with copper posts at the peripheries. Third, a build-up film lamination is formed on the top side of the substrate interposer, with the copper posts embedded inside the build-up film completely at...