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Latency Agnostic Memory Controller with Command Scoreboarding

IP.com Disclosure Number: IPCOM000248472D
Publication Date: 2016-Dec-05
Document File: 3 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a centralized method that performs scoreboarding on the diverse set of commands that access diverse memory technologies, deterministic memory technologies, and non-deterministic memory technologies. This article presents the novel method as command scoreboarding.

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Latency Agnostic Memory Controller with Command Scoreboarding

Known solutions cannot incorporate diverse memory technologies within the same memory channel. Current memory controllers assume (1) a uniform set of parameters for memory technology and (2) deterministic a priori known latencies. Some of the new technologies have non-deterministic command processing times. As several competing memory technologies become available, combining one or more of these memory technologies might be more beneficial for some applications, rather than a single memory technology. A memory controller must be modified to handle a diverse set of timing parameters including non-deterministic command response times.

The novel contribution is a centralized method that performs scoreboarding on the diverse set of commands that access diverse memory technologies, deterministic memory technologies, and non-deterministic memory technologies. This article presents the novel method as command scoreboarding .

Command scoreboarding employs a centralized method, borrowed from the scoreboarding of dynamic instructions in processor cores, to track and schedule commands to memory types with different latencies. The inherently out-of-order nature of scoreboarding allows younger independent commands behind stalled older command to proceed.

Scoreboarding can lead to more powerful memory controllers for two main reasons: (1) complex transactions can be supported to perform powerful high-level functionality by using the command scoreboard like a microcode memory, and (2) interdependencies between data from the various memory types can be supported.

Figure: High-level organization of a memory controller with command scoreboarding. Red and blue shading represent two different memory types with different latencies. The system stores commands accessing each of the memory types together in the central command array. Banks within each memory type have the associated statuses recorded in registers within the scoreboard. Buses within each memory type and common buses have the associated status stored in registers within the scoreboard.

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The above figure is a high-level illustration of the proposed command scoreboarding scheme. The command scoreboard method replaces the command request and response queues in conventional memory controllers with a centralized scoreboard structure. The scoreboard also contains structures that track the status of various resources such as memory banks and buses.

The process follows:

1. Transaction requests arrive at the memory controller 2. System inserts transaction requests into the transaction request queue (TQ_REQ)

3. System selects requests from the request queue 4. System decomposes the requests into commands in the command array within the scoreboard. This includes decoding and setting the appropriate fields for the inserted command 5. System selects the commands from the command array for access to the memories. One method to...