Browse Prior Art Database

Method to Find Chip Level LVS Power Shorts

IP.com Disclosure Number: IPCOM000248481D
Publication Date: 2016-Dec-06
Document File: 5 page(s) / 58K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is method to find chip level Layout Versus Schematic (LVS) power shorts

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Page 01 of 5

Title

Method to Find Chip Level LVS Power Shorts

Abstract

Disclosed is method to find chip level Layout Versus Schematic (LVS) power shorts.

Problem

Bigger chips lead to more complex, bigger grids, with more wiring. Among these, identifying shorts is often difficult. Identifying the cause of the short is time consuming and results in time lost (in critical path to mask house).

Figure 1: Current process

Solution/Novel Contribution

The novel contribution is a method to find chip level Layout Versus Schematic (LVS) power shorts.

Method/Process

Figures and 3 represent the proposed solution.


Page 02 of 5

Figure 2: Proposed method

Figure 3: Special method for running LVS on "glass box"

Definition of Priority Areas


1. Evaluate Power Grid Locations


2. Set "Glass Box" = Overlap region

Exclude single grid areas (for shorts between two different power domains)


Page 03 of 5

Figure 3: Steps 1 and 2

Alternative "Glass Box" Identification

1. Identify "shorting" IP in past technology and draw box around problem IP

2. Identify "problem area" in chip and draw box around area most likely to see shorts


• High routing density

• Custom routing

• Custom IP

Figure 3: Chip IP distribution

Figure 4: Proposed Method - "glass box" priority area


Page 04 of 5

Figure 5: Proposed Method - Use all available markers

1. Merge all wiring from top level into the priority area

2. Use label/PIN shape "markers" to "flag" the shorted nets. Information annotation can be used from "schematic" side...