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Precisely Timed Signal Emphasis for Good Signal Integrity in High Speed Circuits

IP.com Disclosure Number: IPCOM000248482D
Publication Date: 2016-Dec-06
Document File: 2 page(s) / 16K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to improve the processes for meeting duty cycle and jitter specifications for high speed circuits. The solution comprises an assist circuit consisting of a well-known enabled-inverter with the enable transistors on the inside (i.e., drain connected to output) and configured in such a way so as to isolate the miller cap effect from output node to the input.

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Title

Precisely Timed Signal Emphasis for Good Signal Integrity in High Speed Circuits

Abstract

Disclosed is a method to improve the processes for meeting duty cycle and jitter specifications for high speed circuits. The solution comprises an assist circuit consisting of a well-known enabled-inverter with the enable transistors on the inside (i.e., drain connected to output) and configured in such a way so as to isolate the miller cap effect from output node to the input.

Problem

For high speed signaling, in which the rise/fall times of signals are comparable to the half period of the signal, it is very difficult to get the signals to go rail-to-rail across corners. This is especially difficult when the loads are large. Clocks need to be shipped to several places and require buffers over long distances. Clocks need to be manipulated (e.g., muxes, dividers, clock skip circuits etc.), resulting in more distortion of the signal. These challenges and limited solutions result in difficulties in meeting duty cycle and jitter specifications.

Solution/Novel Contribution

The novel contribution is an assist circuit consisting of a well-known enabled-inverter with the enable transistors on the inside (i.e., drain connected to output) and configured in such a way so as to isolate the miller cap effect from output node to the input. The assist circuit is in parallel with a main circuit (e.g., an inverter).

Method/Process

The approach is a pre-emphasis of the signal by the assist circuit of a stage in a chain of circuits, exactly at the point of parasitic miller coupling from subsequent stage.

The enable inputs for positive and negative Field Effect Transistors (PFET and NFET) are shorted and timed such that it is set up in time to enable the output transition. The assist feature thus allows a clean transition of the stage.

The enable input begins to disable the stage when the output transition has r...