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Method and System for Providing an Array Based Test Structure for Static Random-Access Memory (SRAM) Mismatch Measurement with Aging Effect

IP.com Disclosure Number: IPCOM000248666D
Publication Date: 2016-Dec-22
Document File: 4 page(s) / 99K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for measuring static random-access memory (SRAM) cell mismatch by writing the same data in bitline pair. The resulting stored data depends on the relative strength of the left and right half cells. In a perfectly matched SRAM, the resulting distribution of the data (0 or 1) should be evenly distributed. The device mismatch due to processing or aging effects causes one side to be stronger than the other, thus shifting the data pattern distribution. In addition, changing write voltage level also changes the impact factors of each device that is mismatched.

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Method and System for Providing an Array Based Test Structure for Static Random-Access Memory (SRAM) Mismatch Measurement with Aging Effect

As semiconductor technology scales down, the cell stability of static random-access memory (SRAM) becomes more problematic due to large device variations leading to device mismatch. Therefore, a measurement of cell mismatch is vital for characterizing the process technology. A simple way of measuring device mismatch is probing a single cell. However, single cell measurement is misleading because it cannot represent a whole array. Another issue to be considered is the SRAM layout and an SRAM cell is very sensitive to layout pattern and usually has its own design rule. Thus, the actual SRAM layout should be used in implementation and measurement for a more accurate array estimation.

Further, the analog based measurement techniques using external test equipment makes it difficult to be used as an on-chip monitoring circuit. Also, most of the existing mismatch measurement techniques measure read current of SRAM cell or drain current of a selected transistor at pads using external equipment device and mismatch is measured statistically involving additional circuitry for measurement purposes.

FIG. 1a and 1b illustrate impact of mismatch on Static Noise Margin (SNM).

Figure 1a

2

SNM High : Force Q, Measure QB

: f(M2, M4, M6)

SNM Low

: Force QB, Measure Q : f(M1, M3, M5)

Q

Q B

Figure 1b

As illustrated in FIG. 1a and 1b, two SNM curves are independent to each other. SNM high is a function of right devices (M2, M4, M6) and SNM low is a function of left devices (M1, M3, M5). Hence, mismatch is to be measured for accurate SNM estimation.

Disclosed is a method and system for measuring SRAM cell mismatch by writing the same data in bitline pair. The resulting stored data depends on the relative strength of the left and right half cells. In a perfectly matched SRAM, the resulting distribution of the data (0 or 1) should be evenly distributed. The device mismatch due to processing or aging effects causes one side to be stronger than the other, thus shifting the data pattern distribution. In addition, changing write voltage level also changes the impact factors of each device that is mismatched.

Thus, the method and system directly uses the actual SRAM array for mismatch measurement and measures the mismatch of different device combinations without additional circuitry.

The basic principle of measuring SRAM cell mismatch is writing the same data in bitline pair and reading the generated data after write operation. The mismatch in SRAM cell determines the data after write operation. Even if the generated data is a function of all six transistors, they have different impact factor. These impact factors can be controlled by changing the write voltage level. By changing write voltage level, the method and system isolates the devices under test from the rest.

The method and system, then, measures the mismatch in write path i...