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# Method of Projecting the Effect of FET Source and Drain Resistances on Inverterâ€™s Effective Drive Current and Delay

IP.com Disclosure Number: IPCOM000248722D
Publication Date: 2016-Dec-29
Document File: 2 page(s) / 34K

## Publishing Venue

The IP.com Prior Art Database

## Abstract

Effect of FET source/drain resistance change on inverter's effective drive current and delay

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1

Method of Projecting the Effect of FET Source and Drain Resistances on Inverter’s Effective Drive Current and Delay

* If a FET’s source resistance is 30 W more than predicted and the FET’s drain resistance is 50 W more than predicted, how much % degradation it would cause FET’s effective drive current for inverter?

* To improve a FET’s effective drive current for inverter by 1%, how much one has to reduce the FET’s source resistance and how much one has to reduce the FET’s drain resistance?

* What is the impact of a change in FET’s source and drain resistances on inverter’s DC Reff?

Equation (1) below gives the effect of FET source/drain resistance change on the effective drive current of a FET:

(1)

Equation (2) below predicts the change of the FET's effective drive current caused by a change of FET source/drain resistances:

(2) In equations (1) and (2), I

eff,ref is the effective drive current of a reference/base FET (for which  = 0), and

(3) In equation (3), g

m = (I

d,sat,ref - I

low,ref )/(½V

dd ) and g

ds = (I

d,sat,ref - I

high,ref )/(½V

dd ) are average trans-conductances,

2

and r s

is the change in source resistance, and and r d

is the change in drain resistance. (r > 0 when a resistance r increases; r < 0 when the resistance r decreases.)

Equation (4) below predicts the effect of FET source/drain resistance changes on inverter's delay:

(4)

, and are for a reference inverter.

Equation (5) below shows the change of inverter's delay caused by a change of FET sou...