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Low cost substrate manufacturing method & structure without carrier

IP.com Disclosure Number: IPCOM000248740D
Publication Date: 2017-Jan-04
Document File: 3 page(s) / 196K

Publishing Venue

The IP.com Prior Art Database

Abstract

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Low cost substrate manufacturing method & structure without carrier

Summary

Disclosed is an Embedded Trace Substrate (ETS) using a carrier without core material and

manufacturing method thereof. In conventional method, a carrier including core material is

provided to form ETS. In our invention, new carrier without core material is provided. The

carrier comprises Cu-layers double side coated and adhesive between the Cu-layers.

The carrier does not waste core material after separation. In addition, it is not necessary to use

expensive process (tail-less process) for Ni-Au surface finish and to perform Open & Short

(OS) test, so that cost reduction can be achieved.

Description

Fig. 2 ~ 11 shows a manufacturing process of present invention.

Referring now to Fig. 2, providing a carrier phase. The carrier can include a carrier top side

metal, a carrier bottom side metal and an adhesive between the metal layers. The carrier top

side metal and the carrier bottom side metal are detachable from the adhesive. The carrier top

side metal and the carrier bottom side metal are preferably copper.

Fig. 3 shows forming M1 patterning phase. The conductive pattern layer is formed on both

sides of the carrier.

Fig. 4 shows insulation phase. The insulation layer is formed on the upper and lower sides of

the carrier. Prepreg (PPG) is preferable.

Referring now to Fig. 5, a plurality of via holes is formed on the upper and lower insulation

layer. The via holes are formed by laser processing, drilling, or other suitable means.

Referring now to Fig. 6. The photoresist layer (dry film) is laminated on the carrier top side

and the carrier bottom side. The photoresist layer can be selectively developed on the

insulation to form M2 pattern.

Low cost substrate manufacturing method & structure without carrier

Referring now to Fig. 7, a plurality of the via holes and opening formed by photoresist

patterning are plated with conductive metal, Cu is preferable. Subsequently, the photoresist

l...