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Multi-Mode PCIE Interface with Busy Contention Handling

IP.com Disclosure Number: IPCOM000248763D
Publication Date: 2017-Jan-06
Document File: 2 page(s) / 130K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a multi-mode Peripheral Component Internet Express (PCIE) interface with "busy" contention handling. This PCIE interface comprises three different task modes: a mainline task mode, a quick-mode execution, and a recovery execution mode.

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Multi-Mode PCIE Interface with Busy Contention Handling

When trying to access hardware via Peripheral Component Internet Express (PCIE) networks, the issued command can produce a variety of results. Normally, only one operating system mode attempts to retry sending or acquiring the data; however, when running in a multi-mode environment in which different modes require different responses, the process requires different logic to handle the responses from the PCIE network.

When running a number of tasks across multiple processors in which each has dedicated desired requirements, a multi-mode PCIE interface that can adjust to the caller requirements is imperative. Typically, a PCIE interface can be sent and forgotten, and if there are not any credits, one typically spins to wait. In a system that is particularly prone to PCIE hang ups, it becomes necessary to differentiate the PCIE interface to not increase the severity of the sympathy sickness on the machine.

The novel contribution is a multi-mode PCIE interface with “busy” contention handling. This PCIE interface comprises three different task modes: a mainline task mode, a quick-mode execution, and a recovery execution mode.

The first task mode is a mainline task mode in which users prefer the PCIE transaction completes, otherwise it leads to higher-level time-outs and failures. If the return code from the interface is “busy”, indicating that the network cannot handle the transaction, then the code delays for about 15.2 microseconds and then tries the PCIE network again. The code retries until the maximum number of configurable retries is hit. Then, the system passes the return code to the mainline transaction and takes the appropriate action. If the return code during the main line task is an error, then the system reads the status out. If an error occurs on the link of the PCI address (i.e., “space is not valid”), this indicates a problem that requires internal cleanup. If the status is blocked or in-recovery, it means that, a larger recovery action is in place; analysts put out...