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Intelligent software detector of SoC system bus hang when access IP registers without clock

IP.com Disclosure Number: IPCOM000248973D
Publication Date: 2017-Jan-25
Document File: 4 page(s) / 66K

Publishing Venue

The IP.com Prior Art Database

Abstract

System hang due to CPU access register without clock is quite hard to debug for system engineers. Usually it takes a lot time for engineers to find out which clock causes such issue. This paper proposes an intelligent software detector of SoC system bus hang, which can make such issue debug quite simple and catch the error clock automatically. It can save engineers quite a lot time and eventually make the system more stable.

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Title: Intelligent software detector of SoC system bus hang when access IP registers without clock

Abstract:

System hang due to CPU access register without clock is quite hard to debug for system engineers. Usually it takes a lot time for engineers to find out which clock causes such issue. This paper proposes an intelligent software detector of SoC system bus hang, which can make such issue debug quite simple and catch the error clock automatically. It can save engineers quite a lot time and eventually make the system more stable.

Details:

In normal SoC designs, the system may hang when CPU tries to access (Read/Write) an external IP registers if the IP Clock is not enabled. It is because usually the IP Register Access bus has to wait for a valid READY signal from the target IP block. The target IP block can’t generate a valid READY signal if the IP clock is not enabled. Thus, if the IP clock is not enabled, then the system bus keeps waiting and hang, as well as the CPU.

This issue is hardly to debug in software system once it happens because CPU is hang and system just stops running without any error information prompted.

This solution is intended to intelligently detect such issue whenever the CPU is accessing the IP Register without the clock is enabled and telling users the helpful debug information. It can tremendously save the system engineer’s debug time for such type issue. And HW is hardly to do such things automatically but this software solution can help to do it intelligently instead of HW.

The exemplary implementation of this solution includes follows steps:

Step 1: System Setup during Booting

·         Build IP list table

The elements include IP module register base address, register size, IP module index. This information can be got from the SoC Reference Manual or Datasheet and it is SoC specific, different SoCs may build different tables.

·         Build IP module clock tables.

The elements include IP module index and all required clocks to access the register. It’s SoC specific and the information can be got from SoC Reference Manual or Datasheet. At the same time, it’s also OS dependant. For example, for ARM Linux platform supporting Device Tree, the clock table information can be got from Device Tree DTB file.

usdhc1: usdhc@02190000 {

            compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";

            reg = <0x02190000 0x4000>;

            interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

            clocks =...