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REFLECTION CANCELLATION DESIGN WITH BURIED RESISTOR FOR DOUBLE DATA RATE MEMORY SYSTEM

IP.com Disclosure Number: IPCOM000249115D
Publication Date: 2017-Feb-07
Document File: 7 page(s) / 559K

Publishing Venue

The IP.com Prior Art Database

Related People

Yang Wu: AUTHOR [+5]

Abstract

A reflection cancellation design is provided for double data rate types three and four (DDR3/4) control/address/command (C/A) signal lines to improve waveform quality and performance of a memory system. Series resistors are added in the memory chip branch of a daisy chain topology and are implemented via buried resistor technology for improved layout spacing and production feasibility. The DDR C/A lines have high signal quality and speed.

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Copyright 2017 Cisco Systems, Inc. 1

REFLECTION CANCELLATION DESIGN WITH BURIED RESISTOR FOR DOUBLE DATA RATE MEMORY SYSTEM

AUTHORS: Yang Wu

Wenbin Ma Jie Tong

Elvis Zhang Shenzhi Miao

CISCO SYSTEMS, INC.

ABSTRACT

A reflection cancellation design is provided for double data rate types three and

four (DDR3/4) control/address/command (C/A) signal lines to improve waveform quality

and performance of a memory system. Series resistors are added in the memory chip branch

of a daisy chain topology and are implemented via buried resistor technology for improved

layout spacing and production feasibility. The DDR C/A lines have high signal quality and

speed.

DETAILED DESCRIPTION

In double data rate types three and four (DDR3/4) systems,

control/command/address (C/A) signals result in a bottleneck design. Each C/A signal

requires the use of several memory chips as loading chips. In a single rank error-correcting

code (ECC) system, the number of loading chips is nine. This number can be up to thirty-

six in an ECC dual inline memory module (DIMM) system. The multi-loading topology

causes heavy reflection issues. As a result, performance worsens when the system runs at

higher speeds. This phenomenon leads to limitations on the memory chip number and

system speed.

In current DDR3/4 designs, daisy chain topology is used to produce/propagate a

C/A signal. For each receiver chip, there is a small branch from the daisy chain, which

leads to reflections on the daisy chain and repeating reflections on the small branch. Figure

1 below illustrates an example current C/A signal topology for memory design with nine

Copyright 2017 Cisco Systems, Inc. 2

loading chips. In this example, T0a = 100mil, T0b = 4500mil, T1-T8 = 300mil, Ttt = 1000

mil, and Tb = 30mil. The performance of this topology is not good at high speeds.

Figure 1

Figure 2 below illustrates a blown-up view of a junction of a branch of the daisy

chain.

Figure 2

P0-P2 are junction points of the branch. The solid green line illustrates the

waveform from the central processing unit (CPU) side, and the dashed green line illustrates

the corresponding reflection at the T branch. The solid red line is the full reflection from

the synchronous dynamic random access memory (SDRAM) side, and the dashed red line

Copyright 2017 Cisco Systems, Inc. 3

is the corresponding reflection from the T branch point. When the waveform propagates

from the memory controller side, a reflection occurs at point P1. The attenuated waveform

continues advancing along the daisy chain. As illustrated by the dashed green line, there is

also a negative reflection moving back in the direction of the memory controller.

Because the memory receiver side has high impedance, a full reflection occurs at

SDRAM U1, and another reflection occurs at point P1 (red lines). The negative reflection

propagates back to the memory chip side and the attenuated reflection continues forward

in the two directions of the daisy chain. Successive reflections overla...