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Method of Multi-Variable Process Sensitivity Mapping and Predictive Analysis

IP.com Disclosure Number: IPCOM000249118D
Publication Date: 2017-Feb-07
Document File: 2 page(s) / 29K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for multi-variable process sensitivity mapping and predictive analysis on wafer processing data which gives headlights on potential impacts to functional operation and/or yields.

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Method of Multi -Variable Process Sensitivity Mapping and Predictive Analysis

Disclosed is a method for multi-variable process sensitivity mapping and predictive analysis on

wafer processing data which gives headlights on potential impacts to functional operation and/or

yields. This creates a predictive link between process steps, their parameters, and functional

behavior. Semiconductor wafer fabrication requires hundreds of processing steps for today’s

chips. Each process step has a large amount of measurements associated with it, and many have

a specification range which must be maintained and is closely monitored throughout the entire

fabrication process. For example, a dry etch step may have the following parameters monitored:

pressure, gas flows, RF power levels, DC bias, reflected DC power, match box settings, wafers

processed since last clean, end-point time, and Residual Gas Analyzer results often used for

end-point. In a modern fabrication, this data is collected and stored in real time (1 Hz or faster),

thus creating hundreds of data points of data for each wafer and process step. Likewise, there are

many metrology measurements (e.g., film thickness, alignment, critical dimension widths, etc.)

and in-line electrical test parameters. What has been difficult to predict is the effect of a

confluence of specific process step variations together on functional circuits or in-line test

parameters. Most in-spec variation is just fine across most circuits; however, it has been

observed where the combined effect of some changes contribute to significant parametric drift,

fails at test, or in the field, which was not expected. These correlations can be found with many

statistical techniques such as: partial least squares regression or principal component regression.

Additionally, a link between these process confluences and circuit timing tools used at chip

design time could be beneficial.

Step #1: Monitor and Alert

1. Monitor and log process step data. Compare data to specifications and historic results to

measure their variation across wafers as they move through the fabrication.

2. Create a nomenclature to capture the relevant parameters for these process steps, an example

could be:

Wafer A = P 1

(5) 2

, P 2

(2)

4

, P 3

(1) -10

, P 4

(7)-2

…. P n

(y) x

Wafer B = P 1

(5)+1

, P 2

(2)+3

, P 3

(1) -5

, P 4

(7)-4

…. P n

(Y)

x

Where P 2

(3) -4

is process...