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Passive Contact Solution for SOI FinFET

IP.com Disclosure Number: IPCOM000249183D
Publication Date: 2017-Feb-08
Document File: 6 page(s) / 267K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a new process and contact structure to resolve the contact issue in Silicon on Insulator (SOI) Fin Field Effect Transistor (FinFET) technology.

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Title Passive Contact Solution for SOI FinFET Abstract Disclosed is a new process and contact structure to resolve the contact issue in Silicon on Insulator (SOI) Fin Field Effect Transistor (FinFET) technology. Problem Silicon on Insulator (SOI) technology, as a major node, shows many advantages such as low parasitic capacitance and low standby power. A passive device such as a bipolar transistor needs to be fabricated in the bulk region. The topography between the SOI Fin and bipolar transistor leads to a serious contact process margin issue. For SOI Fin Field Effect Transistor (FinFET) technology, this issue is more serious than SOI Ultra Thin Body (UTB). Existing solutions have several issues. The topography issue for all the downstream process, especially contact process, is very challenging. In addition, the costs are high due to implantation designs for different platforms, and the mask layers needed. Further, the contact topography in SOI FinFET technology is more severe due to topography. Solution/Novel Contribution The novel contribution is a new process and contact structure to resolve the contact issue. The solution includes:

• Contact structure • Integration method • Bipolar device structure

Figure 1: New art: Integration Method

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Method/Process The following figures represent the components and process for this solution. Figure 2: Step 1

Figure 3: Step 2

Figure 4: Step 3

Figure 5: Step 4

Figure 6: Step 5

Figure 7: Example Embodiment a)

b) cladding...