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Precise Merging Translation Queue in a Slice-Based Processor

IP.com Disclosure Number: IPCOM000249317D
Publication Date: 2017-Feb-16
Document File: 2 page(s) / 83K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a precise merging translation queue in a slice-based processor. To prevent multiple Effective to Real Address Translation (ERAT) misses to the same page from filling the ERAT Miss Queue (EMQ) and causing redundant ERAT reload requests for the same translation, the approach is to compare the Effective Address (EA) of the ERAT miss to existing EMQ entries.

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Precise Merging Translation Queue in a Slice-Based Processor

General computing super scalar computer cores are organized in a common way, dividing the work of processing instructions into specific compartments, units. In its most basic form, known in the art, these units include:

1. Instruction Fetching Unit (IFU) 2. Instruction Dispatch Unit (IDU) 3. Instruction Sequencing Unit (ISU) 4. Fixed Point Unit (FXU)/Vehicle Transceiver Unit (VXU) 5. Load Store Unit (LSU)

The LSU is the focus of this disclosure. The LSU retrieves data from the memory hierarchy, beginning with a local L1 cache and extending as far down in the hierarchy as needed to find the requested data and place in the General Purpose Register (GPR) or a Vector Register (VR). The LSU stores data from these registers into the memory and handles the effective address (EA) to real address (RA) translations as required to communicate with lower levels of hierarchical memory. When the system presents an instruction to the LSU, it first presents it load or store request by means of an effective address (i.e., the address from the program). However, a real address is needed to communicate with the rest of the memory hierarchy.

The system can perform the address translation from effective to real in many ways, well known to the art. One of the fastest ways is to use an Effective to Real Address Translation (ERAT) Content Addressable Memory (CAM). In one step, an ERAT can change an effective address into a real address (the details of which are outside the scope of this discussion). When an ERAT "hits", it performs this translation.

If the ERAT misses, then the system must reload the ERAT with more current information to enable the translation. These ERAT misses tend to be rare, assuming the ERAT has a robust design that only rarely allows misses. The reloading of information in the ERAT to allow it to hit can take a relatively long time, especially if the information is not contained in a local Translation Lookaside Buffer (TLB), but instead resides in the memory hierarchy, in which case a translation reload could require hundreds of cycles. The system marks ERAT misses in the ERAT Miss Queue (EMQ), while the Memory Management Unit (MMU) locates the correct EA to RA translation and the ERAT is reloaded.

The novel contribution is a method to prevent multiple ERAT misses to the same page from filling the EMQ and causing redundant ERAT reload requests for the same translation. The approach is to compare the EA of the ERAT-miss to existing EMQ entries.

For this comparison, the method uses a subset of the address, which ensures uniqueness, namely EA (35:39). These bits are chosen because these are most significant bits (MSB) bits above the range of the possible page sizes chosen to be implemented in this architecture (e.g., 16M 64k, 4k pages), but any quantity of bits can be used. When new ERAT misses match existing EMQ entries EA (35:39), the system can merge the new misses onto the existin...