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# Method of Dynamic Power Floor Planning Based on Early Design Data Using Ohms/Sq Calculation

IP.com Disclosure Number: IPCOM000249359D
Publication Date: 2017-Feb-20
Document File: 8 page(s) / 300K

## Publishing Venue

The IP.com Prior Art Database

## Abstract

Disclosed is a method of dynamic power floor planning based on early design data using ohms/square calculation.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 25% of the total text.

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Method of Dynamic Power Floor Planning Based on Early Design Data Using Ohms/Sq Calculation

Power optimization tools exist on the market in various forms today. One of the biggest

drawbacks are their limitations; as of today, most of them require a hefty amount of legwork

being done prior to use. The proposed innovation is dealing with the DC portion of the power

delivery and will work prior to physical symbols being created. A system lead could have an

idea of where the processors in a large back planer may go, and use this tool to figure out the

total square area for the power delivery. Using that information, the system lead will be able to

determine if they have enough surface area to support the design.

Raw card design is a complicated process. The puzzle of fitting everything in a

condensed area in a minimal number of signal and power layers can be daunting. To add to the

pressure, if a non-standard material or board stack is used for the design, the materials may need

to be ordered months in advance of having the design complete. The biggest problem with

having to order the materials in advance is the unknowns of the design. These unknowns may

force a design change, making it impossible to build the card on time or without increased cost.

For example, if the Physical Design Team (PD team) has not looked at each of the processor’s

power domains because the voltage regulators are not in the design yet, there is a potential for

increased cost. These unlooked-at domains may require extra layers to be added to the board. If

the order for the material has already been submitted, this could create a major issue; materials

may not be available for purchase or the increase in cost may require the team to scrub the

features because of a missed cost point.

In some cases, it may not be known that the number of layers needs to increase until the

post physical design simulation happens. The simulation may be a week or two before the card is

supposed to be manufactured. Compound this problem over a handful of designs that make up a

system, and the probability for a problem is very high. Today there are tools in place that can

help determine and fix some of these issues. The problem is they tend to require that physical

symbols are created and placed in some configuration, the cross-section or layer count of a board

is defined, the logical connections are done, the shapes are drawn in the board file, and the

technology assumptions are complete. Most of these items are not done until the physical design

phase of a project, which can be too late to find out about the problems. Pressure increases when

a problem is found because most of the solutions only identify the problem. They do not offer a

possible solution. An example: if a power domain is failing its minimum voltage specification

by 10%, meaning it is 10% under what the device requires. That is all the tool reports, it does not

offer a suggestion to increase the cross section given the wiring o...