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CELL FOR STACKED MULTILEVEL CONVERTERS FOR LIMITING SHORT CIRCUIT CURRENTS

IP.com Disclosure Number: IPCOM000249462D
Publication Date: 2017-Feb-28
Document File: 9 page(s) / 249K

Publishing Venue

The IP.com Prior Art Database

Abstract

A cell or electrical network for multilevel converters for limiting short circuit currents is disclosed herein. The network comprises two terminals, at least one loop comprising energy storage elements between the two terminals, at least one inductor, at least two single or composed fully controllable non-latching switches capable of bidirectional voltage blocking when open and at least one additional energy storage element having at least one of its two terminals not directly connected with any of the controllable switches. Advantageously the cell limits the short circuit currents at both the AC and DC terminals of the whole converter, uses less expensive switches and minimizes the risks of explosions.

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CELL FOR STACKED MULTILEVEL CONVERTERS FOR LIMITING SHORT CIRCUIT CURRENTS

BACKGROUND

 

The present disclosure relates generally to multilevel converters and more particularly to a cell for stacked multilevel converters for limiting short circuit currents.

Generally, series-connected or stacked modular multilevel converters are used for medium voltage direct current (MVDC) or high voltage direct current (HVDC) marine, subsea and land based applications. These circuits require techniques for fault tolerance, short circuiting and explosion.  There are various conventional techniques used for fault tolerance and limiting current to cells in multilevel converters.

Conventional techniques include using a crow-bar solution to divert current away from the switches, using switches which can block unidirectional voltage when open or network of inductors, capacitors and energy storage devices. These conventional techniques provide fault tolerance and limit current to the cells by either complex realization based on traditional storage and semiconductor technology, by solutions based on by-passes and damage-limitation equipment or via special rugged semiconductors. However, these conventional techniques suffer from the disadvantage of current flowing in an arm composed by several cells in series directly flowing also in the main switch that commutates at relatively low frequency.

Further, during fault and/or incorrect control events, loops composed by capacitors and faulty switches are formed inside cells. Those fault loops imply sudden discharge of large capacitor energies into the faulty switches, which can explode and endanger the survivability of the whole converter if curing means such as explosion boxes are not adopted. 

It would be desirable to have an improved technique for fault tolerance in multilevel converters. 

BRIEF DESCRIPTION OF DRAWINGS

Figure 1 depicts the simplest embodiment of the cell or electrical network for multilevel converters disclosed herein.

Figure 2 depicts an embodiment of the cell having two structures connected in anti-series to realize a composed cell that can synthesize vcell of both polarities.

Figure 3 depicts another embodiment of the cell that synthesizes vcell of both polarities via an internal diode bridge.

Figure 4 depicts another embodiment of the cell without a diode bridge.

DETAILED DESCRIPTION

A cell or electrical network for multilevel converters for limiting short circuit currents is described herein. The network comprises two terminals, at least one loop comprising energy storage elements between the two terminals, at least one inductor, at least two single or composed fully controllable non-latching switches capable of bidirectional voltage blocking when open and at least one additional energy storage element having at least one of its two terminals not directly connected with any of the controllable switches.

 

The voltage at the two terminals is a continuous function of time whose first total time...