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Voltage regulator with off-chip inductor

IP.com Disclosure Number: IPCOM000249730D
Publication Date: 2017-Mar-28
Document File: 9 page(s) / 495K

Publishing Venue

The IP.com Prior Art Database

Abstract

Data center equipment such as CPUs, GPUs, etc., are subject to rapid and wide variation in demand. In the presence of such variation in demand, voltage of the power supply to the equipment can fluctuate beyond specification, resulting in malfunction or damage. Power supply in data centers is designed to respond quickly to changes in demand, while being regulated within a narrow range of voltage. High switching frequency of a voltage regulator (VR) enables improved dynamic response. The VR is often placed on the same board as the load. Such placement limits the switching bandwidth and thereby, dynamic performance of the VR. To improve switching bandwidth, the VR is placed closer to the load, e.g., on the package, chip or die. However, integration of the magnetics, e.g., inductors that comprise the VR, on a chip or die is difficult due to the larger size of magnetic components. Another challenge is the coupling between the magnetic field of an on-chip inductor and high-speed signal lines within the load. This disclosure describes techniques that retain the VR on the chip with provision for inductors to be placed off chip.

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Voltage regulator with off-chip inductor

ABSTRACT

Data center equipment such as CPUs, GPUs, etc., are subject to rapid and wide variation

in demand. In the presence of such variation in demand, voltage of the power supply to the

equipment can fluctuate beyond specification, resulting in malfunction or damage. Power

supply in data centers is designed to respond quickly to changes in demand, while being

regulated within a narrow range of voltage. High switching frequency of a voltage regulator

(VR) enables improved dynamic response. The VR is often placed on the same board as the

load. Such placement limits the switching bandwidth and thereby, dynamic performance of the

VR. To improve switching bandwidth, the VR is placed closer to the load, e.g., on the package,

chip or die. However, integration of the magnetics, e.g., inductors that comprise the VR, on a

chip or die is difficult due to the larger size of magnetic components. Another challenge is the

coupling between the magnetic field of an on-chip inductor and high-speed signal lines within

the load. This disclosure describes techniques that retain the VR on the chip with provision for

inductors to be placed off chip.

KEYWORDS:

● Integrated voltage regulator

● Data center power supply

● DC-DC converter

● Power delivery network

BACKGROUND

Fig. 1: Topologies for on-board voltage regulation

Fig. 1 shows example topologies for on-board voltage regulation. In Fig. 1(a), a power

supply voltage Vin , e.g., in the range of 5-12 V, is converted to a logic-level voltage Vout, e.g.,

about 1 Volt, that is supplied to a load such as a CPU, GPU, etc. The DC-DC conversion from

power-supply to logic-level is performed using multiple parallel circuits (N circuits 1021-102N)

driven by pulse-wave modulated waveforms PWM1 through PWMN. Each circuit includes driver

metal-oxide semiconductor transistors, e.g., DrMOS1 through DrMOSN and magnetic

components, e.g., inductors (1061-106N). Fig. 1(b) illustrates a two-stage architecture in which

an intermediate bus converter (110) converts a voltage Vin in the 40-60 V range to a power

supply voltage Vdd in the 5-12 V range, which in turn is converted to the logic-level voltage Vout

using the topology of Fig. 1(a).

On-board voltage regulators, as shown in Fig. 1, have shortcomings such as:

1. DC heating losses that can cause a greater than 1% drop in efficiency.

2. Reduced performance due to AC impedance, e.g., on-board PCB resistance and

inductance, which necessitates insertion of decoupling capacitances under or

inside the package. Due in part to this, component density of on-board VRs is

low.

3. Low switching frequency which limits the dynamic response of the VR.

There are configurations that address these shortcomings of the on-board voltage

regulator by integration of VR into the package, chip or die containing the load. Two such on-

chip designs are shown in Fig. 2.

Fig. 2: Topologies for on-chip voltage regulation

In Fig. 2, the enclosures in red color (202) are...