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Sigma-shape Bottom EPI for V-FinFET

IP.com Disclosure Number: IPCOM000249841D
Publication Date: 2017-Apr-14
Document File: 4 page(s) / 121K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a design for a sigma-shape recess and a source/drain (S/D) EPI as a means of reducing both the thermal budget and resistance in the Vertical Fin Field Effect Transistor (finFET) process.

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Title Sigma-shape Bottom EPI for V-FinFET Abstract Disclosed is a design for a sigma-shape recess and a source/drain (S/D) EPI as a means of reducing both the thermal budget and resistance in the Vertical Fin Field Effect Transistor (finFET) process. Problem In the Vertical Fin Field Effect Transistor (finFET) process on record (POR), the bottom epitaxy (EPI) is not aligned with the Fin, thus creating a large contact resistance. Attempting to reduce Ron requires a high thermal budget. Vertical finFET has drawn a lot of attention for the future node development; however, significant difference/challenges are found in the design and integration. For example, the current POR scheme for junction formation uses implant or epitaxy for bottom source/drain (S/D) and must use anneal to drive dopant towards the fin. It is desired to have the S/D EPI overlap with the Fin, to enable reductions in both the thermal budget and resistance. Solution/Novel Contribution The novel solution is a design for a sigma-shape recess and an S/D EPI. The sigma- shape EPI has a tip protruding toward the bottom of Fin, thus reducing the misalignment as well as the thermal budget needed for driving in dopant. Compared to other techniques that etch the cavity in lateral direction, it is easier to control in the automatic level. This solution for a sigma-shaped bottom S/D integration with vertical finFET comprises:

• Forming the Fin to be used as a channel in the vertical direction • Forming a sacrificial spacer around the Fin and between Fins • Forming a sigma-shaped bottom S/D recess and EPI between Fins

– The sigma wet can start right after spacer Reactive Ion Etch (RIE) – Alternatively, after spacer RIE, a shallow direction Silicon (Si) recess is

done, followed by a wet sigma etch – A lower temperature rapid thermal annealing (RTA) to further drive dopant

into Fin/Channel and form overlap The sigma-shape S/D, although similar in the drawing, is very different from the sigma- shape used in the previous planner device for embedded...