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Side-Anchoring Silicon-on-Nothing

IP.com Disclosure Number: IPCOM000250006D
Publication Date: 2017-May-15
Document File: 5 page(s) / 37K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a simple method to form Fin dielectric isolation from bulk substrate. The flow generates a fin Field Effect Transistor (FET) or nanosheet/nanowire Silicon-on-Nothing (SON) structure to prevent sub-fin leakage.

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Title Side-Anchoring Silicon-on-Nothing Abstract Disclosed is a simple method to form Fin dielectric isolation from bulk substrate. The flow generates a fin Field Effect Transistor (FET) or nanosheet/nanowire Silicon-on- Nothing (SON) structure to prevent sub-fin leakage. Problem Sub-fin leakage is a top issue for Fin Field Effect Transistor (FET) devices. Dielectric isolation has been proposed to solve/improve the sub-Fin leakage issue. Prior proposed schemes include:

• Partial isolation (dielectric under channel only) • Full isolation (dielectric under channel and S/D) • Full isolation is usually considered better for better • Leakage control • Simple junction integration

Solution/Novel Contribution The novel solution is a simpler method to form Fin dielectric isolation from bulk substrate. The end structure is like Fin on Silicon on Insulator (SOI). The simple flow generates a finFET or nanosheet/nanowire Silicon-on-Nothing (SON) structure. A FinFET with bottom dielectric isolation combines the benefits of both FinFET and SOI, providing a unique technology. Method/Process The method for method of forming semiconductor fins isolated from the substrate consists of:

1. Forming a sacrificial layer on a substrate, followed by a channel semiconductor layer, followed by a cap layer

2. Forming insulating pillars through the cap, channel, and sacrificial layers 3. Removing the cap layer 4. Forming spacers adjacent the insulating pillars, said spacers of thickness to

expose the channel layer surface between adjacent spacers 5. Anisotropically etching the channel material down to the sacrificial layer, leaving

channel semiconductor fins under the spacers 6. Removing the sacrificial layer between and under the channel semiconductor fins 7. Filling the region u...