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Novel Method for Enforcing Design for Manufacturability (DFM) Compliance at the Standard Cell, or Block Level

IP.com Disclosure Number: IPCOM000250007D
Publication Date: 2017-May-15
Document File: 2 page(s) / 42K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for enforcing Design for Manufacturability (DFM) compliance at the standard cell or block level by accounting for logic utilization context at a normalized full chip level of 1cm^2. By analyzing standard cells and blocks in the context of complete chip usage, the method allows designers to incorporate DFM compliance at a correct construction level.

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Title Novel Method for Enforcing Design for Manufacturability (DFM) Compliance at the Standard Cell, or Block Level Abstract Disclosed is a method for enforcing Design for Manufacturability (DFM) compliance at the standard cell or block level by accounting for logic utilization context at a normalized full chip level of 1cm^2. By analyzing standard cells and blocks in the context of complete chip usage, the method allows designers to incorporate DFM compliance at a correct construction level. Problem In current methods, used industry wide, Design for Manufacturability (DFM) compliance is based on a Poisson yield model to enforce criteria at chip level. This method does not scale at a standard cell or block level. Standard cell and IP designers are tasked with a multitude of factors while attempting to meet power, performance, and area constraints. A method is needed to provide designers with a method for quantifying DFM while single blocks are still under development. Solution/Novel Contribution Proposed is a novel method for enforcing Design for Manufacturability (DFM) compliance at the standard cell or block level by accounting for logic utilization context at a normalized full chip level of 1cm^2. The solution is a method wherein area and logic utilization is defined, thus providing context to single cell or block macros. This percentage is then considered during manufacturing and analysis (MAS) scoring evaluation. Designers can incorporate chip utilization parameters into the MAS score. Such parameters affect the final MAS score and prove valuable in quantifying IP. To achieve this, the solution developers analyzed numerous full chip designs and decomposed these chips to enable the assignment of an area percentage to all standard cell logic as well as non-logic areas. This data can be further extracted for all combinational and sequential logic. Figure: Cell/Block Level DFM Scoring

Method/Process The novel flow enables designers to qua...