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SINGLE ROOT INPUT/OUTPUT VIRTUALIZATION (SR-IOV) BASED FUNCTION SLICE ACCELERATOR WITH DIRECT MEMORY TRANSFER

IP.com Disclosure Number: IPCOM000250070D
Publication Date: 2017-May-25

Publishing Venue

The IP.com Prior Art Database

Abstract

The present disclosure relates to a lookaside hardware accelerator architecture of a PCIe add-on card physical formality and can be used to build an offload engine for a virtual Switch (vSwitch) or Virtual Network Function (VNF). The acceleration processor uniquely operates on a functional basis. It is a lookaside model, and the acceleration processor behaves as "hardened" function library with respect to the corresponding "software" function in a "software" library. Each individual function can employ Single Root Input/Output Virtualization (SR-IOV) to communicate with a specific "virtual machine." The "hardware" function library is hosted in a PCIe/SRIOV add-on card and functions as a co-processor to the server or host processors. Advantageously, the acceleration processor only carves out the software function desired to be accelerated, hence only minimum hardware resources are required resulting in a lower cost solution. The acceleration processor is individual function based and thus reusable across a product line. It is essentially a hardened software function. The acceleration processor only deals with the packet header metadata and thus reduces the amount of data to be processed lowering the activity and power consumption. Also, there is no requirement to re-build the acceleration processor in each new release.

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SINGLE ROOT INPUT/OUTPUT VIRTUALIZATION (SR-IOV) BASED FUNCTION SLICE ACCELERATOR WITH DIRECT MEMORY TRANSFER

ABSTRACT

The present disclosure relates to a lookaside hardware accelerator architecture of a PCIe add-on card physical formality and can be used to build an offload engine for a virtual Switch (vSwitch) or Virtual Network Function (VNF).  The acceleration processor uniquely operates on a functional basis.  It is a lookaside model, and the acceleration processor behaves as “hardened” function library with respect to the corresponding “software” function in a “software” library. Each individual function can employ Single Root Input/Output Virtualization (SR-IOV) to communicate with a specific “virtual machine.”  The “hardware” function library is hosted in a PCIe/SRIOV add-on card and functions as a co-processor to the server or host processors.  Advantageously, the acceleration processor only carves out the software function desired to be accelerated, hence only minimum hardware resources are required resulting in a lower cost solution.  The acceleration processor is individual function based and thus reusable across a product line.  It is essentially a hardened software function.  The acceleration processor only deals with the packet header metadata and thus reduces the amount of data to be processed lowering the activity and power consumption.  Also, there is no requirement to re-build the acceleration processor in each new release.

 

DETAILED DESCRIPTION

Again, the present disclosure relates to a lookaside hardware accelerator architecture of a PCIe add-on card physical formality and can be used to build an offload engine for a virtual Switch (vSwitch) or Virtual Network Function (VNF). 

The acceleration processor uniquely operates on a functional basis.  It is a lookaside model, and the acceleration processor behaves as “hardened” function library with respect to the corresponding “software” function in a “software” library. Each individual function can employ Single Root Input/Output Virtualization (SR-IOV) to communicate with a specific “virtual machine.”  The “hardware” function library is hosted in a PCIe/SRIOV add-on card and functions as a co-processor to the server or host processors.

Advantageously, the acceleration processor only carves out the software function desired to be accelerated, hence only minimum hardware resources are required resulting in a lower cost solution.  The acceleration processor is individual function based and thus reusable across a product line.  It is essentially a hardened software function.  The acceleration processor only deals with the packet header metadata and thus reduces the amount of data to be processed lowering the activity and power consumption.  Also, there is no requirement to re-build the acceleration processor in each new release.

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