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Atomic Page Table Entry RC Update Backtracking

IP.com Disclosure Number: IPCOM000250099D
Publication Date: 2017-Jun-01
Document File: 2 page(s) / 73K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method and system is disclosed for updating reference and change bits in a nested radix address translation using backtracking mechanism.

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Method and System for Updating Reference and Change Bits in a Nested Radix Address Translation using Backtracking Mechanism

Abstract

A method and system is disclosed for updating reference and change bits in a nested radix address translation using backtracking mechanism.

Description

In power architecture, hardware is responsible to atomically set a reference (R) and change (C) bits in a page table entry (PTE) using a load reserve (LARX) and store conditional (STCX) instructions mechanism with the power memory hierarchy. The PTE that maps a guest effective address to a guest real address makes hardware components to set the reference and change bits accordingly for load/store operations. The R and C bits updated in nested radix translation involves three page table entries such as, PTE#1 (the host PTE maps the guest PTE), PTE#2 (the guest PTE itself of the data access), and PTE#3 (the host PTE itself of the data access). However, this mechanism gets tricky when changing the guest PTE, which results in mapping same area of memory by a host PTE to a host real address. Consequently, setting the R and C bits in the guest PTE changes the virtualized guest real page. So there exists a need for a method and system that sets the change bits in the host PTE that maps to the guest PTE guest real address (gRA).

Disclosed is a method and system for updating R and C bits in a nested radix address translation using backtracking mechanism. The method and system sets the change bits in the host PTE that maps to the guest PTE gRA. Accordingly, a radix table walk requests one memory access at a time per table walk, and generates new addresses from each step in the translation. Subsequently, host real address (hRA) is saved on an initial walk in order to set C bit in the PTE#1. Thereafter,...