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METHOD OF HIGH VOLTAGE ISOLATION IN SEMICONDUCTOR IC PACKAGES

IP.com Disclosure Number: IPCOM000250142D
Publication Date: 2017-Jun-05
Document File: 3 page(s) / 132K

Publishing Venue

The IP.com Prior Art Database

Abstract

A system and method that implements a safe routing of high voltage (HV) nets of voltage regulator (VR), to reduce dielectric breakdown risks and to improve the safety and reliability of semiconductor IC packages are disclosed. Accordingly, the method routes and limits the HV net in isolated vertical channels on the semiconductor IC package. The HV net and the HV return net go from the ball grid array (BGA) directly up to the VR on package that is placed on top of the package in isolated channels. This completely eliminates the lateral routing requirements of the HV nets to micro-vias stacking. A minimum spacing may be maintained between the HV nets and the low voltage nets to eliminate any dielectric breakdown risk. Also vertical overlap between high voltage nets and low voltage nets is avoided to eliminate vertical breakdown risk.

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METHOD OF HIGH VOLTAGE ISOLATION IN SEMICONDUCTOR IC PACKAGES

ABSTRACT

A system and method that implements a safe routing of high voltage (HV) nets of voltage

regulator (VR), to reduce dielectric breakdown risks and to improve the safety and reliability of

semiconductor IC packages are disclosed. Accordingly, the method routes and limits the HV net

in isolated vertical channels on the semiconductor IC package. The HV net and the HV return net

go from the ball grid array (BGA) directly up to the VR on package that is placed on top of the

package in isolated channels. This completely eliminates the lateral routing requirements of the

HV nets to micro-vias stacking. A minimum spacing may be maintained between the HV nets

and the low voltage nets to eliminate any dielectric breakdown risk. Also vertical overlap

between high voltage nets and low voltage nets is avoided to eliminate vertical breakdown risk.

BACKGROUND

Voltage regulators (VR) deliver regulated power to a load, with minimum loss and also

maintain a constant voltage to a processor during transient response. VR on-chip solutions have

come up, in which the voltage regulators are integrated into the semiconductor IC package. The

input voltage of the VR could be 12V or even as high as 60V. This is significantly higher than

the typical package voltages that take up values such as 1V, 1.2V, 1.8V up to 2.5V. This order of

magnitude higher voltage of the VR introduces a new set of challenges to package design. With

VR integrated into the IC package, high voltage (HV) nets and low voltage nets are

simultaneously present on the package. This may expose the package build up and core dielectric

materials to risk of dielectric breakdown. The guidelines on PCB safety rules and net

classification address the risk at the PCB level. Accordingly, PCB materials are constantly

evaluated and tested for hi-pot, dielectric breakdown and safety. Also, net classifications on the

PCB define the isolation and clearances needed in PCB design. Package manufacturing design

rules define minimum dimensions and spacing of various package features...