Browse Prior Art Database

Method and Computer Program for End to End Logic Verification for Complex Multilevel Systems

IP.com Disclosure Number: IPCOM000250176D
Publication Date: 2017-Jun-07
Document File: 2 page(s) / 102K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for End to End Logic Verification for Complex Multilevel Systems is disclosed.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

1

Method for End to End Logic Verification for Complex Multilevel Systems

A method for End to End Logic Verification for Complex Multilevel Systems is disclosed.

Disclosed is a method for end to end logic verification for complex multilevel systems.

Full connectivity verification of complex electronic designs requires access and evaluation of several logic topologies and their connectivity. These topologies typically reside across multiple schematic files, each one corresponding to a particular function or section of the system. In some instances, the component or function being reviewed is at an early stage of definition or development. Typically, at an early stage of development, the component or function’s specification is documented at a high level in non-schematic form, such as spreadsheets, pin data files, and so on. Traditionally, manual and visual inspections are the mechanisms to assess the correct implementation of end-to-end connectivity of signals, from original driver to end receiver, across independent design files or documents. This process is tedious, inefficient and time consuming, and prone to errors.

The solution described herein is a system, method, and computer program product that allows importing the different sections of the system being designed in one giant canvas. Within this canvas, each signal contains the end-to-end connectivity. This path can be graphically visualized for inspection across all packaging levels. Further, the tool and method allows importing pre-production specification documents for comparison against the schematic implementation to verify their accuracy. Any discrepancies or errors are reported by the tool. Thus, automating the whole logic verification process, without the need for manual reviews of predefined circuit requirements. A complex electronic system is composed of multiple components such as cards, chip carriers, cables and so on. Each component has self-contained circuit logic that is defined and documented by its own set of design files or documents. Components...