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Ultra Thin Substrate

IP.com Disclosure Number: IPCOM000250207D
Publication Date: 2017-Jun-12
Document File: 3 page(s) / 215K

Publishing Venue

The IP.com Prior Art Database

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Ultra Thin Substrate

Background

Nowadays, the need for thin substrate is dramatically increasing in the semiconductor

industry. In Fig. 1(a), a conventional flip-chip single metal substrate (fc-SMS) is adopted

with a base copper layer of 10 um and a total height of 110 um; in Fig. 1(b), the fc-SMS is

assembled into a package with a die mounted and molded underfill (MUF) formed on the

front surface and solder balls attached to the back surface.

Fig. 1(a) the conventional flip-chip single metal substrate (fc-SMS); (b) the fc-SMS assembled into a package

However, the conventional fc-SMS cannot satisfy the current need in the semiconductor

market, which requires a much thinner substrate. Difficulties in the fabrication of ultra thin

substrate still remain unsolved in terms of manufacturing and assembly processes.

Description

The subject invention discloses an ultra thin substrate structure and the manufacturing

processes thereof. This ultra thin substrate with a low manufacture cost has the advantages of

enabling fine lines and spaces and enhanced trace protection and peel strength by using a

second copper core laminate (CCL) carrier.

The structure of the ultra thin substrate is shown in Fig. 2(a) on a second CCL carrier. The

total height of the ultra thin substrate is reduced to 50 um. In Fig. 2(b), the ultra thin substrate

is assembled into a package with a die mounted and molded underfill (MUF) formed on the

front surface and solder balls attached to the back surface.

Fig. 2 (a) the ultra thin substrate in the subject invention; (b) the ultra thin substrate assembled into a package

One process flow with a second CCL carrier is shown in Fig. 3 to fabricate the ultra thin

substrate in the subjected invention. The process flow includes the following steps in

sequence: (1) preparing a first carrier with CCL material; (2) forming a first metal (M1)

patterning; (3) forming a Prepreg (PPG) or Ajinomoto Build-up Film (ABF) lamination on

the M1 patterning; (4) forming holes by laser drilling; (5) forming a second metal (M2)

patterning inside the holes and on the lamination; (6) applying flash etching to form the M2

circuitry patterning; (7) forming bottom solder resist (SR) and undergoing half curing; (8)

Ultra Thin Substrate

attaching a second carrier and undergoing half curing; (9) detaching the first carrier and

splitting the structure into two identical parts; (10) applying flash etching to form circuitry

and,...