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Novel methodology for warpage reduction.

IP.com Disclosure Number: IPCOM000250215D
Publication Date: 2017-Jun-12
Document File: 3 page(s) / 116K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a methodology to remove or top-up specific layer(s) on the wafer backside to reduce the warpage.

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This is the abbreviated version, containing approximately 100% of the total text.

Title Novel methodology for warpage reduction Abstract Disclosed is a methodology to remove or top-up specific layer(s) on the wafer backside to reduce the warpage. Problem Forty (40)nm Non-Volatile Memory (NVM) has a lithography overlay out-of-spec issue. Wafer warping causes improper focusing during lithography, so NVM devices tend to have higher warpage due to a more complicated wafer backside film stack. Solution/Novel Contribution The novel solution is a methodology to remove or top-up specific layer(s) on the wafer backside to reduce the warpage. Method/Process The following figures represent the solution in a preferred embodiment. Figure 1: Process flow

Figure 2: Film warpage library for material screening

Figure 3: Backside strip approach Choose a suitable chemical to remove the specific film(s) that causes wafer warping.

Figure 4: Top up backside film approach Choose a suitable chemical to remove the specific film(s) that causes wafer warping.

Advantages over Previous Solutions The disclosed methodology to remove or top-up specific layer(s) on the wafer backside to reduce the warpage is a systematic solution for warpage reduction. It does not impact the front side film scheme. In addition, it is production-friendly and ready for implementation.