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A Chamber Free and Low Capacitance Interconnect for 7nm and Beyond Nodes

IP.com Disclosure Number: IPCOM000250216D
Publication Date: 2017-Jun-12
Document File: 2 page(s) / 184K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use a new material with properties that are similar to an ultra-low K (ULK) material to reduce damage and improve capacitance in semiconductor manufacturing.

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Title A Chamfer Free and Low Capacitance Interconnect for 7nm and Beyond Nodes Abstract Disclosed a method to use a new material with properties that are similar to an ultra-low K (ULK) material to reduce damage and improve capacitance in semiconductor manufacturing. Problem The first issue addressed in this disclosure is wire resistance. Within wafer (WiW) uniformity in post Vx Reactive Ion Etching (RIE) causes significant variation in wire resistance from center to edge. This NU% causes time dependent dielectric breakdown (TDDB) failure with poor values for “beta”. The second issue is that via-chamfer control that is required for reliability performance is more difficult with a trench first metal hard mask (MHM) scheme that does not have any via plug material to protect via bottom profile. The process should be optimized for inter-metal shorts and TDDB. Figure 1: Via-chamfer control issue

Solution/Novel Contribution The solution is to mitigate the above challenges using a new material with properties that are similar to an ultra-low K (ULK) material. Method/Process

Figure 3: Components and process for implementing the solution

Figure 4: Commercially available organic low-k materials that can be used for this method

Advantages over Previous Solutions This method reduces etch/ash related damage at side wall. Organic film is better for Chemical Mechanical Planarization (CMP) stop and can minimize CMP-related damage. The air gap formed between the dielectrics layer can further...