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Cycle Execution During Unit Power-Down and/or Power-Up Sequencing

IP.com Disclosure Number: IPCOM000250239D
Publication Date: 2017-Jun-15
Document File: 3 page(s) / 76K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to effectively utilize the period during the power-up and power-down phases of the functional units of a semiconductor device by executing functional code during the power-ramp sequences. The novel method allows productive execution during power-down and power-up sequencing and minimizes the period during which no instructions can be executed on either side of a power-off or power-reduction sequence.

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Cycle Execution During Unit Power-Down and/or Power-Up Sequencing

Disclosed is a method to effectively utilize the period during the power-up and power-down

phases of the functional units of a semiconductor device by executing functional code during the

power-ramp sequences. The novel method allows productive execution during power-down and

power-up sequencing and minimizes the period during which no instructions can be executed on

either side of a power-off or power-reduction sequence.

Integrated circuit excess power dissipation is an issue facing semiconductor design and

manufacturing. Functional units of a semiconductor device are frequently powered down.

Power supply stability issues limit the rate at which power can be stepped up or down. Quickly

switching off one die or unit on a die can adversely affect the neighboring devices unless great

care is taken to limit the transient currents.

The novel contribution is a method that allows productive execution during power-down and

power-up sequencing and minimizes the period during which no instructions can be executed on

either side of a power-off or power-reduction sequence.

The basis of novelty is the execution of functional code during the power ramp sequences. The

power ramps are typically done over thousands of clock cycles with relatively small voltage

steps up or down to minimize power supply noise events on neighboring units, as mentioned

above. The total duration of an entire power supply reduction or inflation is nominally 1e4 to

1e5 clock cycles.

This solution focuses on the power supply reduction side of the power saving approach, but the

same technique also applies to the power-up side. For example, assume a 1V nominal and a

power savings reduction mode, "sleep", at 0.6V. The intent of that mode of operation is not only

power dissipation reduction, but also the preservation of logic states during the sleep mode to

allow reasonably fast resumption of normal operation without requiring a large amount of

scanning-in of data.

In the power supply descent from 1V to 0.6V, the first drop is to perhaps 0.95V and the supply is

allowed to settle for many hundreds of cycles before dropping again to 0.9V, etc. Generally, the

first of the se...