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Instruction Level Marking for Hang Buster Mechanism in SMT Microprocessor

IP.com Disclosure Number: IPCOM000250254D
Publication Date: 2017-Jun-19
Document File: 3 page(s) / 137K

Publishing Venue

The IP.com Prior Art Database

Abstract

In current SMT (simultaneous multi-threading) cores, a single processors instruction scheduling resources can be shared among multiple threads. An SMT core can hang if these critical resources are consumed by one thread, preventing another thread from making forward progress. This invention describes a mechanism whereby specific instructions in the instruction stream can be marked as needing special handling, and can enter the ISU (Instruction Scheduling Unit) hang buster to perform actions that prevent the thread from hanging.

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Instruction Level Marking for Hang Buster Mechanism in SMT Microprocessor

In current SMT (simultaneous multi-threading) cores, a single processors instruction scheduling resources can be shared among multiple threads. These resources, such as (but not limited to) issue queue entries, completion table entries, and register mapper entries, are required to manage instructions as they are executed by the processor. These resources are allocated when new instructions are dispatched into the processors, and are consumed while the instructions are 'in-flight' and their results are still speculative. These resources are released at various points during the instructions execution or when the instruction is flushed.

An SMT core can hang if these critical resources are consumed by one thread, preventing another thread from making forward progress. The current method to handle such a thread-starvation hang requires the core to wait for millions of cycles to see if forward progress has been made. If no forward progress has been made on a thread, then it will initiate a core flush-request to try to flush out each thread. Execution resumes when the flush has been processed and resources consumed by the flushed thread are freed up.

However, this approach has a few problems. First, this method can cause significant performance loss if these hangs occur frequently due to harmonic behavior between the threads. If one thread consistently blocks another thread by consuming all resources, the starved thread will repeatedly hang for millions of cycles before the hang-busting action is performed. Additionally, since it takes millions of cycle to detect the hang condition before the core can perform the flush request, it is very hard to debug when and where the hang started.

This invention describes a mechanism whereby specific instructions in the instruction stream can be marked as needing special handling, and can enter the ISU (Instruction Scheduling Unit) hang buster to perform actions that prevent the thread from hanging. Certain instructions can be more likely to cause a hang for many reasons. The instruction may have restrictive execution constraints, or may need to wait for specific resources to be available, or the instruction may be dependent on some other very long latency action. When such instructions are encountered in a multi-threaded processor, it can be beneficial to perform a

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specific action, changing the processor behavior while this specific instruction is 'in-flight', rather than waiting for millions of cycles to detect a hang.

An instruction can be marked at fetch time by the IFU (Instruction Fetch Unit). This instruction-marking indicates that the instruction needs special-handling by the processor and propagates with the instruction as it moves through the core. The debug marked instruction can be detected at va...