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Embedded Die Package with Coreless Substrate using PID

IP.com Disclosure Number: IPCOM000250269D
Publication Date: 2017-Jun-21
Document File: 6 page(s) / 377K

Publishing Venue

The IP.com Prior Art Database

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 35% of the total text.

Embedded Die Package with Coreless Substrate using PID

Background

Embedded die substrate has advantage to reduce PKG height. However there are many

problems about heat management, difficulty of mass production, and thermal fatigue.

The invention discloses the method of manufacturing embedded package with dual-process in

order to solve the problems. Our invention is able to not only reduce package size by using

embedded die but also increase productivity by using dual-process. Moreover simplifying the

process, it is able to reduce manufacturing cost.

Description

Fig. 2 ~ 8 shows a process of manufacturing one embodiment.

Referring now to Fig. 2, providing a detach core phase. The detach core can include core,

detachable adhesive on top & bottom side, and metal-layers on top & bottom side. The core

Embedded Die Package with Coreless Substrate using PID

can include SUS plate, FR4 plate, or polymer reinforced plate as examples. The metal layer is

preferably copper. Fig. 2a shows a detach core having detachable adhesive. Fig. 2b shows a

detach core having detachable adhesive and metal layer.

Fig 3 shows die-attach phase. The adhesive is disposed on the detach core. The back side of

the semiconductor die is disposed on the adhesive. The adhesive may be set by thermal, light,

UV, etc.

In Fig. 3b, the adhesive is preferably TIM(Thermal Interface Material). The TIM is able to

effectively transfer thermal generated from semiconductor die.

Fig. 4 shows PID(photo imageable dieletectric) lamination phase. PID material characteristic

is similar with solder resist which is generally used to protect outer surface of a substrate.

PID can be patterned by photo, at which portion exposed by photo is rigid. In addition, it can

be more hardened by additional UV or thermal treatment.

A PID layer is deposited over the detach core so as to cover the semiconductor die and the

detach core.

Fig. 5 shows forming openings phase. A plurality of opening is formed through PID layer

down to pads of the semiconductor die using a photo patterning process. A mask layer (dry

film is preferable) is laminated on the PID layer, at which is needed to form opening. The

mask is patterned to form openings. The PID that is not covered by the mask is exposed to

ultraviolet light (UV). The portion of PID exposed by the UV has been developed. After

exposure, the mask and the developed portion of PID is eliminated. The remaining PID layer

may be additionally cured by heat, UV, or other suitable means. The PID layer is cured and

act as encapsulation.

Fig. 6 shows forming the first conductive pattern layer phase. Plating can be applied on the

openings of the carrier top & bottom side. The plating can be made of conductive material

such as copper.

Fig. 7 shows forming solder resist (SR) layer over the pattern for electrical isolation. SR is

deposited over the pattern so as to cover or protect the pattern. A portion of SR layer can be

removed by a photo patterning to expose the pads for componen...