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Clock Phase Error Checker

IP.com Disclosure Number: IPCOM000250497D
Publication Date: 2017-Jul-25
Document File: 5 page(s) / 63K

Publishing Venue

The IP.com Prior Art Database

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This is the abbreviated version, containing approximately 38% of the total text.

Clock Phase Error Checker

Some digital logic circuits utilize multiple clocks, and those clocks are multiples of each other. In order

for those circuits to operate correctly, the multiple clocks must all initialize in the proper phase

relationship, and stay in that phase relationship for the lifetime of the circuit’s operation. This invention

provides an error checking circuit to ensure that the clocks initialize to, and remain in, the proper phase

relationship. This improves error detection and fault isolation of the system which utilizes the circuit.

For clocks that are multiples of each other, we can define a known relationship between them, and

design error checkers, using simple counters and XOR circuits, to detect if the clocks fail to initialize

correctly, or if they ever fall out of the known relationship with each other. I am not aware that this

check is currently being performed.

As an example, assume a system which has a reference clock, and three clock blocks which generate

clock phases which have the same frequency as the reference clock (DIV1_CLK), one-half the frequency

(DIV2_CLK), and one-fourth the frequency (DIV4_CLK).

In the following diagrams, time runs from left to right. The index row is for reference. All latches are

assumed to be falling edge triggered.

Reset is asserted until index 6. When reset is de-asserted, the TWGs output their clocks in the following

refclk period.

When reset is asserted, the divX inverting latches are clocked with the refclk, and are held in reset. Once

reset is lifted, they are clocked with their corresponding divX clock, and invert every cycle.

The check disable latches are clocked with the refclk, and are used to block the error check until the

inverting latches start their first inversion cycle. The compare counter is clocked with the refclk, and is

used to determine what compare value to expect every cycle.

The outputs of the div1 and div2 inverting latches are XORed, as are the outputs of the div2 and div4

inverting latches. The div1_div2_err checks that the XOR value is true when the compare count is 0, 1, 4,

or 5, and false when 2, 3, 6, or 7. The div2_div4_err checks that the XOR is true when the compare count

is 1, 2, 3, or 4.

The example immediately below is a good machine example. The clocks start as expected, and are in

sync. The error checker does not assert.

index 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

reset 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

refclk 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

div1_clk 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

div2_clk 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

div4_clk 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

div1_inv_latch 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

div2_inv_latch 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

div4_inv_latch 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

div1L_XOR_div2L 0 0...