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Making Low Resistive Contact by Using Early Dummy Contact Scheme

IP.com Disclosure Number: IPCOM000250531D
Publication Date: 2017-Jul-28
Document File: 2 page(s) / 155K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an early dummy contact process. The method forms an early source/drain (SD) contact based semiconductor transistor.

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Title Making Low Resistive Contact by Using Early Dummy Contact Scheme Abstract Disclosed is an early dummy contact process. The method forms an early source/drain (SD) contact based semiconductor transistor. Problem A method is needed to enable wrap-around-contact without contact reactive ion etch (RIE) damage. Solution/Novel Contribution The novel solution is an early dummy contact process. The method forms an early source/drain (SD) contact based semiconductor transistor. The core idea is to move contact patterning from post-replacement metal gate (RMG) to pre-RMG, and form SD epi after the contact pattern (Early Contact). Next, the method forms dummy oxide and dummy Si (or SiGe) after SD epi formation, which can be removed at the final contact process (i.e., CA/CB), which enables wrap-around-contact without contact RIE damage, and the trench silicide (TS) process can be skipped. Method/Process The method to form early SD contact based semiconductor transistor is consists of the following steps:

1. FIN & shallow trench isolation (STI) formation 2. Dummy PC (gate) formation 3. First ILD formation 4. P-type SD contact patterning 5. P-type SD epi formation 6. Dummy Contact formation in PSD region 7. Second (inter-layer dielectric) ILD formation 8. N-type SD contact patterning 9. N-type SD epi formation 10. Dummy Contact formation in n-type source drain (NSD) region 11. Third ILD formation 12. Replacement Gate formation 13. ILD formation 14. Contact Patterning 15. Removal of...