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Method to Mitigate CTE Mismatch in Printed Circuit Boards

IP.com Disclosure Number: IPCOM000250570D
Publication Date: 2017-Aug-03
Document File: 2 page(s) / 115K

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The IP.com Prior Art Database

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Method to Mitigate CTE Mismatch in Printed Circuit Boards

Disclosed is a method of adding layered ruthenate particles with a negative linear CTE into

laminate materials used in printed circuit boards (PCBs) to mitigate CTE mismatch with the

copper. These layered ruthenate particles can be modified with a resin bonding agent to improve

adhesion to the laminate matrix and/or a glass bonding functionality.

This method aims to mitigate the CTE mismatch between the laminate and copper in a PCB. This

can be accomplished in one of two ways.

Embodiment 1: Layered ruthenate mixed into laminate resin

Powdered layered ruthenate would be added into the prepreg resin as silica particles are

added in currently. The amount of ruthenate can be tailored to the application and may be

mixed with the silica filler particles to attain the desired properties. The ruthenate

particles have a negative linear coefficient of thermal expansion in temperature regions

relevant for PCB manufacture/operation. For example, the CTE of ruthenate has been

reported to be –115 ppm/K over the range of 200 K to 345 K. The CTE of several

ruthenate variants remain negative up to 500 K. [1] Thus, the ruthenate CTE is far more

negative than the CTE of silica, ~0.55-0.75 ppm/K. In Megtron 7*, for example, silica

makes up 25 wt% of the formulation. Therefore, substitution of all or some of the silica

with ruthenate will result in a lower CTE above the glass transition temperature of the

resin and higher PTH reliability....