Browse Prior Art Database

Alternative Low Cost Cu Post Substrate for HB PoP Application

IP.com Disclosure Number: IPCOM000250913D
Publication Date: 2017-Sep-14
Document File: 3 page(s) / 226K

Publishing Venue

The IP.com Prior Art Database

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 50% of the total text.

Alternative Low Cost Cu Post Substrate for HB PoP Application

Background

Industry developed an integrated circuit (IC) package structure, and in particular, to a side-

by side type package structure comprising a plurality of semiconductor chips that are

vertically and horizontally disposed over a package substrate. In particular, to a PoP

comprising integrated Application Processor (AP), DRAM, and NAND as shown in Fig. 1.

The e-PoP form factor can be reduced about 50%. Also current wire-bonding memory die is

transferred to flip chip device for high signal speed and smaller die form factor.

Fig. 1

Description

Fig. 2

Fig. 2 shows one of embodiments of disclosed package structure.

The first package is provided. The first substrate is general laminate substrate to allow

semiconductor chips for interconnecting with other devices.

The Cu-Post is formed around of perimeter of the first substrate using photo-patterning

process or suitable method. After forming Cu-Post, an encapsulant or molding compound is

deposited around the first substrate and over Cu-post using a compressive molding, transfer

molding or other suitable applicator. After encapsulation, a cavity is formed to accommodate

other semiconductors or packages.

Alternative Low Cost Cu Post Substrate for HB PoP Application

A semiconductor chip (AP) is disposed on the first substrate. The chip includes a bump,

which can includes Cu, solder, Ni, Au, or combination thereof. The semiconductor chip is

electrically connected to the first substrate by the bump.

The second package is provided. The second substrate is general laminate substrate to allow

semiconductor chips (DRAM) for interconnecting with other devices. A semiconductor chip

is disposed on the second substrate. The chip may include a bump, which can includes Cu,

solder, Ni, Au, or combination thereof. The semiconductor chip is electrically connected to

the second substrate by the bump. Encapsulant or molding compounds covers over

semiconductor chip and the second substrate.

The first interconnection is attached on the perimeter of the bottom surface of the second

substrate. The first interconnection may be solder ball, CCSB (Copper Core Solder ball), Cu-

ball, or etc (CCSB is preferable). The second package is disposed on the first substrate. The

vacancy of the first interconnection matches position of the semiconductor chip, which is

surrounded by the first interconnection. The second package is electrically connected to the

first package.

The third package is provided. The third substrate is general laminate substrate to allow

semiconductor chips for interconnecting with other device.

A semiconductor chip (NAND) is disposed on the substrate. The chip may include a bump,

which can includes Cu, solder, Ni, Au, or combination thereof. The semiconductor chip is

electrically connected to the substrate by the bump.

Encapsulant or molding compounds covers over the semiconductor chips and the third

substrate. The second interconnection is at...