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Software Controlled Segmented Cache For Microprocessors Disclosure Number: IPCOM000004627D
Original Publication Date: 2001-Mar-01
Included in the Prior Art Database: 2001-Mar-01
Document File: 2 page(s) / 25K

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Brian G. Lucas: AUTHOR


Software Controlled Segmented Cache For Microprocessors

This text was extracted from a WORD97 document.
This is the abbreviated version, containing approximately 54% of the total text.

Software Controlled Segmented Cache

For Microprocessors

by Brian G. Lucas

Caches are used in microprocessors to decrease the effective latency of memory accesses by taking advantage of the spatial and temporal locality of address sequences. The ability of software to control the mechanisms by which the cache hardware operates varies among cache designs, but is generally minimal. The software control available is usually global, i.e.; the same set of rules is applied to all running programs based on the static properties of the program.

A cache consists of a number of lines that are, in turn, made up of a number of words. When it is determined that a word is not present in the cache (a cache miss), information determined from the address of the word is used to determine the set of lines which are eligible to hold the cached word. The number of lines in the set varies with cache designs, from one in a direct mapped cache to the total number of lines in a fully associative cache. If the number of lines in a set, say N, is more than 1 but less than the total number of lines, the cache is said to be N-way associative.

The term sector has been used previously in the literature to describe a unit of allocation within a cache line. In "sector caches", a cache line is divided into sectors to minimize memory traffic by pre-loading only a sector at a time, while the memory address tags refer to the entire line. We will use a different term, segment, to define "a set of lines that have the same cache miss behavior".

Rudimentary segmented caches exist. For example, a cache may be divided into two segments, one segment reserved for instructions and the other for data. The relative size of each of the two segments is usually fixed at the time the microprocessor is designed. In some cases, the relative proportions of the two segments may be changed by software (e.g., in the M.Core M340 cache design).

In systems where a memory management unit (MMU) is present, often some cache functionality can be controlled based on an address range with granularity based on the page size. This feature has been limited to disabling caching completely for this page or selecting among write-back policies.

To increase performance in real-time systems and to mitigate the effects of large data sets in multimedia applications, more control over the caching algorithms by applications is needed. Real-time systems need to mark certain routines and their associated data as latency critical, and thus give them "priority" access to the cache. Some hardware designs have enabled software to "lock" cache lines once they are loaded.

The effect of large data sets, such as multimedia data, causes problems with current cache designs. Sequencing through a vector of multimedia data whose size is greater than the cache size will completely flush the previously cached data. If the multimedia data is not refer...