Multiplexer using Self-biased FET Devices
Publication Date: 2001-Mar-15
The IP.com Prior Art Database
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Miniaturization of MOS transistor dimensions has been and continues to be the driving force for improving circuit speed, at lower power, and with improved reliability. Scaling (reducing) the horizontal dimensions of transistors, the oxide thickness of the gates (vertical dimensions), etc. in a manner consistent with the electrical characteristics of CMOS devices has been previously described. Maximizing device drive current when the device is "on" is achieved by using low device threshold voltage (Vth) and short channel lengths. The problem is that the combination of a low Vth voltage and a short channel length results in a high leakage current when the device is in the "off" condition. Device design results in a compromise in which a higher threshold voltage and a longer channel length are used for a lower leakage current, sacrificing device current capability. What is needed is a way to continue to miniaturize CMOS while achieving both high device drive current in the "on" state, and low device leakage current in the "off" state. Disclosed is a technique for applying improved FET devices to multiplexer device applications.