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Design for Ultra-Low Skew-Matched Frequency Divider Clock Circuit

IP.com Disclosure Number: IPCOM000004843D
Publication Date: 2001-Jul-10

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a design for an ultra-low skew-matched frequency divider circuit for high-speed clock distributions. The design uses a divide-by-1 complementary metal-oxide semiconductor (CMOS) circuit that delay-matches a divide-by-2 CMOS for clocking applications. In previous designs, the divide-by-2 and the divide-by-1 circuits showed a finite delay mismatch (typically between 10 and 20 ps) that sums linearly with each cascaded stage. The disclosed design provides much more accurate delay matching. This allows a significant reduction of clock skew on the chip, both between different frequency domains and within the same domain if used in the phase locked loop (PLL) feedback path.