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Circuit to Improve I/O Buffer Speed

IP.com Disclosure Number: IPCOM000004844D
Publication Date: 2001-Jul-10

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an impedance control bit translator circuit that improves input/output (I/O) buffer timings. It amplifies the swing of the process, voltage and temperature (PVT) compensated predriver stage of the I/O buffer, thus maximizing the benefits obtainable from the PVT bits. In effect, this circuit speeds up the I/O buffers, improving microprocessor performance.