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More Stable Flip-Flop with Self-biased Circuit Feedback for sub-0.75V Operation

IP.com Disclosure Number: IPCOM000005034D
Publication Date: 2001-Aug-01
Document File: 4 page(s) / 148K

Publishing Venue

The IP.com Prior Art Database

Abstract

Miniaturization of MOS transistor dimensions has been and continues to be the driving force for improving circuit speed, at lower power, and with improved reliability. Scaling (reducing) the horizontal dimensions of transistors, the oxide thickness of the gates (vertical dimensions), etc. in a manner consistent with the electrical characteristics of CMOS devices is described in reference 1: H.B. Bakoglu "Circuits, Interconnections, and Packaging for VLSI", Addison-Wesley Publishing Co. 1990, pages 26-28.