Method of Hybrid devices on SOI
Original Publication Date: 2001-Aug-01
Included in the Prior Art Database: 2001-Aug-01
Body-tied SOI device is critical to eliminate unnecessary floating body effect for SOI application. Current T- and H- gate structures increase loading gate capacitance, resulting in slow performance of the body-tied circuits. Recently, partial trench isolation has been adopted as a body-tied device structure. The suggested invention is the method to make the hybrid devices using partial trench concept. Previous art used separate partial trench mask from full trench mask to create a device with partial trench. Since the trench process is very critical, the partial photo step needs more attention same as full trench photo step. In addition, there is a concern on PR residue inside of one trench hole before fill. These are penalties of the dual trench concept. The partial and full trench area patterned before trench isolation process using silicon thinning process in this invention. Initially, very think SOI is prepared. The Silicon thickness may be 1500A or 2000A. and then PAD oxide and Nitride are deposited on the SOI. Using large full trench area mask, device area, which would have full trench, is opened. And then the Nitride and PAD oxide in the area is etched followed by ashing. And thermal oxide is grown to make the silicon film in the full trench area thin. The remaining silicon thickness under oxide may be 1000A. This thermal oxidation is sometimes required to control silicon thickness even in regular SOI process. After that, the nitride and oxide are removed by wet chemistry. As a result, SOI film with two different thickness is prepared. And then one trench process followed. The thin silicon area has full trench, while thick silicon area has partial trench. And then typical CMOS process followed. The full trench area mask is not critical mask step and so the photo step can be easily implemented. With this concept we could build fully-depleted and partially-depleted SOI devices with body-tied device with partial trench isolation on single wafer.