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Use of N bit Memory for M bit Symbols Disclosure Number: IPCOM000005048D
Original Publication Date: 2001-Aug-01
Included in the Prior Art Database: 2001-Aug-01
Document File: 3 page(s) / 39K

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John Ferrara: AUTHOR [+2]


Use of N bit Memory for M bit Symbols

This text was extracted from a WORD97 document.
This is the abbreviated version, containing approximately 81% of the total text.

Use of N bit Memory for M bit Symbols

John Ferrara)

Raymond P. Voith, Charles Robinson


A typical byte interleaver uses an 8-bit memory, allowing a linear mapping of interleave data positions to memory addresses (See ADSL Finale specification Ch.3 for clarification). The ADSL has a large 24 bit memory, a portion of which is available for the interleaver function. This memory requires a re-mapping of interleave positions to memory addresses since each 24-bit word will contain 3-bytes of interleave data.


The 24-bit memory can be used in a linear fashion by mapping it as follows:

The mapping of the addresses to positions above is not one-to-one. Each address corresponds to 3-bytes of interleave data:

Data 0 (0,0)

Data 1 (0,1)

Data 2 (0,2)

Data 3 (1,0)


Any byte position P, can be mapped into memory with a vector or address as follows:

P (P/3,P%3)

Where the first element is an n bit physical memory address and the second is a 2 bit byte index. The lower 2-bits will be used as an index into the 24-bit word to select the byte to read or write.


The above can be generalized to allow use of N bit memories to store M bit data (M N). The M bit data will be referred to as a symbol. Each location in the N bit memory will be used to hold int(N/M) symbols. An address (AddrNM) will be used to refer to each M bit symbol. One field of the address (AddrN), will specify an address in the N bit memory Another field (AddrM) will select on of the int(N/M) M bit symbols stored in memory at ADDRNM.

We will now generalize from the above example, where N was 24 and M was 8. In general, a vector mapping:

P (V2, V1) (P/3,P%Q)

where Q N/M

Can be used to map M bit symbols to an N bit memory. Note that if Q is not integer, some bits may be unused in this scheme.

Circuits for arithmetic (incrementing, adding and subtracting) on such vectors will be discussed. The circuit is a modification of a normal adder/subtracter/incrementer. In addition, a special circuit allows selective writing of an M bit symbol into an N bit location in the physical memory.

Arithmetic Circuits

Normal arithmetic adder/subtracter/incrementer circuits must be modified to operate in a "special" mode. Operations on the lower vector elements (V1) (used to select a symbol in a sub-field of a memory location must be done with a log2 (M) bit modulus Q adder/subtracter/incrementer which generates a carry/borrow to a normal adder/subtracter/incrementer that operates on the upper vector elements (V2).

Note that memory writes will require first a read and then a write. The N-bits within which the M bit symbol is to be written must first be read, then the M bit symbol within the N bits must be modified, then, finally, the modified N bits must be written back to memory, completing th...