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Flip Chip PBGA Using Only Peripheral Pads Disclosure Number: IPCOM000005284D
Original Publication Date: 2001-Aug-20
Included in the Prior Art Database: 2001-Aug-20
Document File: 2 page(s) / 23K

Publishing Venue


Related People

Burton J. Carpenter: AUTHOR [+4]


Flip Chip PBGA Using Only Peripheral Pads

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Flip Chip PBGA Using Only Peripheral Pads

Burt Carpenter, Chris Clark, Ken Rhyner, Bill Stone

Motorola, Semiconductor Products Sector 3501 Ed Bluestein Boulevard

Austin, Texas 78721

Current flip chip PBGA devices use many (>2) rows of bumps at a relatively course pitch. The interior rows requires advanced substrate design rules, which typically require a premium substrate technology in order to route between the outer pad rows. However, if the device can be designed with only one pad row that routes out, then the substrate could be routed using a lower technology with relaxed design rules for traces, spaces and vias. This would be a significant substrate cost savings. However, this might require a finer bump pitch.

Current FC Design

Proposed FC Design

Multiple FC rows with standard pad drives dense line/spaces

Multi-Layer HDI Substrate

Figure 1: Comparison of conventional flip chip substrate design and “Peripheral Pad Only” design

Single peripheral row with smaller pads allows relaxed lines/space

Simpler “Standard” Substrate

An example of the current style flip chip design is shown in the left hand side of Figure 1. The bump pattern is arranged in 3 rows. In order connect from the second row of pads to the outboard vias, a trace needs to be run between the outermost pad row. The size of these traces and spaces premium require an advanced manufacturing technology, which carries a premium cost.

The left hand side of Figure 1 shows the proposed routing using a tighter pitch bump pads. By tightening the pad pitch, all of the pads can be contained within the outermost row, thus creating a single peripheral row, allowing the substrate to be routed with “standard” substrate technology.