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GENERATION OF CLOCK SIGNALS FOR SWITCHED CAPACITOR NETWORKS

IP.com Disclosure Number: IPCOM000005401D
Original Publication Date: 2001-Sep-24
Included in the Prior Art Database: 2001-Sep-24

Publishing Venue

Motorola

Related People

Authors:
Michael Gay

Abstract

An arrangement (300) for generation of clock signals for switched capacitor networks, particularly in CMOS integrated circuits in smartcards, has a coil (310) for receiving AC power; and a rectifier (M1-M4) having inputs coupled to the coil for converting received alternating power to DC power, wherein the inputs of the rectifier are coupled to outputs of the arrangement whereby signals at the inputs to said rectifier serve as clock signals for switched capacitor networks. The arrangement allows simple and effective generation of clock signals which are well suited to use in switched capacitor networks in CMOS integrated circuits in contact-less smartcards (400), and may be arranged so that excursion of signals at the inputs of the rectifier is constrained to remain within a limit with respect to one of the rectified outputs of the rectifier, whereby conduction in parasitic devices associated with the arrangement may be inhibited.